1/* 2 * Copyright (c) 2009, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * pl011_uart.dev 11 * 12 * DESCRIPTION: PrimeCell UART (PL011) 13 * 14 * This is derived from: 15 * 16 * PrimeCell UART (PL011) Revision: r1p5 by ARM Limited. 17 * (DDI0183_uart_pl011_r1p5_trm.pdf) 18 * 19 */ 20 21device pl011_uart msbfirst ( addr base ) "PL011 UART" { 22 23 constants word_len "Word Length" { 24 bits5 = 0b00 "5 bits"; 25 bits6 = 0b01 "6 bits"; 26 bits7 = 0b10 "7 bits"; 27 bits8 = 0b11 "8 bits"; 28 }; 29 30 constants rx_lvl "Receive interrupt FIFO level" { 31 geq_1_8 = 0b000; 32 geq_1_4 = 0b001; 33 geq_1_2 = 0b010; 34 geq_3_4 = 0b011; 35 geq_7_8 = 0b100; 36 }; 37 38 constants tx_lvl "Transmit interrupt FIFO level" { 39 leq_1_8 = 0b000; 40 leq_1_4 = 0b001; 41 leq_1_2 = 0b010; 42 leq_3_4 = 0b011; 43 leq_7_8 = 0b100; 44 }; 45 46 /* 47 * Standard UART registers 48 */ 49 register DR addr (base, 0x0) "Data Register" { 50 _ 20; 51 oe 1 ro "Overrun error"; 52 be 1 ro "Break error"; 53 pe 1 ro "Parity error"; 54 fe 1 ro "Framing error"; 55 data 8 rw "Data character"; 56 }; 57 58 register RSR_ECR addr (base, 0x4) "UART receive status / error clear" { 59 _ 24; 60 _ 4 rsvd; 61 oe 1 rwzc "Overrun error"; 62 be 1 rwzc "Break error"; 63 pe 1 rwzc "Parity error"; 64 fe 1 rwzc "Framing error"; 65 }; 66 67 register FR addr (base, 0x18) "Flag Register" { 68 _ 23; 69 ri 1 ro "Ring indicator"; 70 txfe 1 ro "Transmit FIFO empty"; 71 rxff 1 ro "Receive FIFO full"; 72 txff 1 ro "Transmit FIFO full"; 73 rxfe 1 ro "Receive FIFO empty"; 74 busy 1 ro "UART Busy (transmit active)"; 75 dcd 1 ro "Data carrier detect"; 76 dsr 1 ro "Data set ready."; 77 cts 1 ro "Clear to send."; 78 }; 79 80 register ILPR addr (base, 0x20) "IrDA Low-Power Counter" { 81 _ 24; 82 ilpdvsr 8 rw "Low power divisor"; 83 }; 84 85 register IBRD addr (base, 0x24) "Integer Baud Rate" { 86 _ 16; 87 divint 16 rw "Integer divisor"; 88 }; 89 90 register FBRD addr (base, 0x28) "Fractional Baud Rate" { 91 _ 26; 92 divfrac 6 rw "Fractional divisor"; 93 }; 94 95 register LCR_H addr (base, 0x2c) "Line Control" { 96 _ 24; 97 sps 1 rw "Stick parity select"; 98 wlen 2 rw type(word_len) "Word length"; 99 fen 1 rw "FIFOs enable"; 100 stp2 1 rw "Two stop bits select"; 101 eps 1 rw "Even parity select"; 102 pen 1 rw "Parity enable"; 103 brk 1 rw "Send break"; 104 }; 105 106 register CR addr (base, 0x30) "Control" { 107 _ 16; 108 ctsen 1 rw "CTS hardware flow control enable"; 109 rtsen 1 rw "RTS hardware flow control enable"; 110 out2 1 rw "Out2 modem status output"; 111 out1 1 rw "Out1 modem status output"; 112 rts 1 rw "Request to send"; 113 dtr 1 rw "Data transmit ready"; 114 rxe 1 rw "Receive enable"; 115 txe 1 rw "Transmit enable"; 116 lbe 1 rw "Loopback enable"; 117 _ 4; 118 sirlp 1 rw "SIR low-power IrDA mode"; 119 siren 1 rw "SIR enable"; 120 uarten 1 rw "UART enable"; 121 }; 122 123 register IFLS addr (base, 0x34) "Interrupt FIFO Level Select" { 124 _ 26; 125 rxiflsel 3 rw type(rx_lvl) "Receive interrupt FIFO level select"; 126 txiflsel 3 rw type(tx_lvl) "Transmit interrupt FIFO level select"; 127 }; 128 129 register IMSC addr (base, 0x38) "Interrupt Mask Set/Clear" { 130 _ 21; 131 oeim 1 rw "Overrun error interrupt mask"; 132 beim 1 rw "Break error interrupt mask"; 133 peim 1 rw "Parity error interrupt mask"; 134 feim 1 rw "Framing error interrupt mask"; 135 rtim 1 rw "Receive timeout interrupt mask"; 136 txim 1 rw "Transmit interrupt mask"; 137 rxim 1 rw "Receive interrupt mask"; 138 dsrmim 1 rw "nUARTDSR modem interrupt mask"; 139 dcdmim 1 rw "nUARTDCD modem interrupt mask"; 140 ctsmim 1 rw "nUARTCTS modem interrupt mask"; 141 rimim 1 rw "nUARTRI modem interrupt mask"; 142 }; 143 144 register RIS addr (base, 0x3c) "Raw Interrupt Status" { 145 _ 21; 146 oeris 1 ro "Overrun error interrupt status"; 147 beris 1 ro "Break error interrupt status"; 148 peris 1 ro "Parity error interrupt status"; 149 feris 1 ro "Framing error interrupt status"; 150 rtris 1 ro "Receive timeout interrupt status"; 151 txris 1 ro "Transmit interrupt status"; 152 rxris 1 ro "Receive interrupt status"; 153 dsrrmis 1 ro "nUARTDSR modem interrupt status"; 154 dcdrmis 1 ro "nUARTDCD modem interrupt status"; 155 ctsrmis 1 ro "nUARTCTS modem interrupt status"; 156 rirmis 1 ro "nUARTRI modem interrupt status"; 157 }; 158 159 register MIS addr (base, 0x40) "Masked Interrupt Status" { 160 _ 21; 161 oemis 1 ro "Overrun error masked interrupt status"; 162 bemis 1 ro "Break error masked interrupt status"; 163 pemis 1 ro "Parity error masked interrupt status"; 164 femis 1 ro "Framing error masked interrupt status"; 165 rtmis 1 ro "Receive timeout masked interrupt status"; 166 txmis 1 ro "Transmit masked interrupt status"; 167 rxmis 1 ro "Receive masked interrupt status"; 168 dsrmmis 1 ro "nUARTDSR modem masked interrupt status"; 169 dcdmmis 1 ro "nUARTDCD modem masked interrupt status"; 170 ctsmmis 1 ro "nUARTCTS modem masked interrupt status"; 171 rimmis 1 ro "nUARTRI modem masked interrupt status"; 172 }; 173 174 register ICR addr (base, 0x44) "Interrupt Clear" { 175 _ 21 mbz; 176 oeic 1 rw1c "Overrun error interrupt clear"; 177 beic 1 rw1c "Break error interrupt clear"; 178 peic 1 rw1c "Parity error interrupt clear"; 179 feic 1 rw1c "Framing error interrupt clear"; 180 rtic 1 rw1c "Receive timeout interrupt clear"; 181 txic 1 rw1c "Transmit interrupt clear"; 182 rxic 1 rw1c "Receive interrupt clear"; 183 dsrmic 1 rw1c "nUARTDSR modem interrupt clear"; 184 dcdmic 1 rw1c "nUARTDCD modem interrupt clear"; 185 ctsmic 1 rw1c "nUARTCTS modem interrupt clear"; 186 rimic 1 rw1c "nUARTRI modem interrupt clear"; 187 }; 188 189 register DMACR addr (base, 0x48) "DMA Control" { 190 _ 29; 191 dmaonerr 1 rw "DMA on error"; 192 txdmae 1 rw "Transmit DMA enable"; 193 rxdmae 1 rw "Receive DMA enable"; 194 }; 195 196 /* 197 * Test registers: only used for integration testing 198 */ 199 register TCR addr (base, 0x80) "Test Control" { 200 _ 29; 201 sirtest 1 rw "SIR test enable"; 202 testfifo 1 rw "Test FIFO enable"; 203 iten 1 rw "Integration test enable"; 204 }; 205 206 register ITIP addr (base, 0x84) "Integration Test Input" { 207 _ 24; 208 txdmaclr 1 rw "Value to drive UARTTXDMACLR"; 209 rxdmaclr 1 rw "Value to drive UARTRXDMACLR"; 210 nuartpri 1 ro "nUARTPRI primary input"; 211 nuartdcd 1 ro "nUARTDCD primary input"; 212 nuartcts 1 ro "nUARTCTS primary input"; 213 nuartdsr 1 ro "nUARTDSR primary input"; 214 sirin 1 ro "SIRIN primary input"; 215 uartrxd 1 ro "UARTRXD primary input"; 216 }; 217 218 register ITOP addr (base, 0x88) "Integration Test Output" { 219 _ 16; 220 ttxdmasreq 1 rw "Intra-chip output UARTTXDMASREQ"; 221 ttxdmabreq 1 rw "Intra-chip output UARTTXDMABREQ"; 222 trxdmasreq 1 rw "Intra-chip output UARTRXDMASREQ"; 223 trxdmabreq 1 rw "Intra-chip output UARTDMABREQ"; 224 tmsintr 1 rw "Intra-chip output UARTMSINTR"; 225 trxintr 1 rw "Intra-chip output UARTRXINTR"; 226 ttxintr 1 rw "Intra-chip output UARTTXINTR"; 227 trtintr 1 rw "Intra-chip output UARTRTINTR"; 228 teintr 1 rw "Intra-chip output UARTEINTR"; 229 tintr 1 rw "Intra-chip output UARTINTR"; 230 nuartout2 1 ro "Primary output nUARTOut2"; 231 nuartout1 1 ro "Primary output nUARTOut1"; 232 nuartrts 1 ro "Primary output nUARTRTS"; 233 nuartdtr 1 ro "Primary output nUARTDTR"; 234 nsirout 1 ro "Primary output nSIROUT"; 235 uarttxd 1 ro "Primary output UARTTXD"; 236 }; 237 238 register TDR addr (base, 0x8c) "Test Data" { 239 _ 21; 240 data 11 rw "Data written to rx / read from tx FIFO"; 241 }; 242 243 /* 244 * Identification registers 245 */ 246 register PeriphID0 ro addr (base, 0xFE0) "Peripheral ID 0" { 247 _ 24 mbz; 248 partnumber0 8 "Should be 0x11"; 249 }; 250 register PeriphID1 ro addr (base, 0xFE4) "Peripheral ID 1" { 251 _ 24 mbz; 252 designer0 4 "Should be 0x1"; 253 partnumber1 4 "Should be 0x0"; 254 }; 255 register PeriphID2 ro addr (base, 0xFE8) "Peripheral ID 2" { 256 _ 24 mbz; 257 revision 4 "Revision of the UART"; 258 designer1 4 "Should be 0x4"; 259 }; 260 register PeriphID3 ro addr (base, 0xFEC) "Peripheral ID 3" { 261 _ 24 mbz; 262 configuration 8 "Should be 0x0"; 263 }; 264 265 regarray CdellID addr (base, 0xFF0) [ 4 ] "Cell ID (should be 0xb105f00d)" { 266 _ 24 mbz; 267 id 8 "PrimeCell identification registers"; 268 }; 269}; 270