1/* 2 * Copyright (c) 2018, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * pci_msix_cap.dev 11 * 12 * DESCRIPTION: PCI MSI-X Capability 13 * 14 * Source: Section 6.8.2. in PCI Local Bus Specification 15 */ 16 17device pci_msix_cap lsbfirst ( addr base ) "PCI MSI-X Capability" { 18 19 // 6.8.2.(1-3) 20 register hdr rw addr( base, 0x00 ) "Capabilities Header" { 21 id 8 "Capability ID"; 22 next 8 "Next Pointer"; 23 tblsize 11 "Message Control - Table Size"; 24 res 4 "reserved"; 25 en 1 "MSI-X enable"; 26 }; 27 28 regtype location "Location" { 29 bir 3 "Base Address Register Index"; 30 offset 29 "Offset"; 31 }; 32 33 register tbl ro addr(base, 0x4) "Table Location" type(location); 34 register pba ro addr(base, 0x8) "Table Location" type(location); 35}; 36 37 38