1/* 2 * Copyright (c) 2008, 2009, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * pci_hdr0.dev 11 * 12 * DESCRIPTION: PCI Type 0 Configuration header 13 * 14 */ 15 16device pci_hdr0_mem msbfirst ( addr base ) "PCI Type 0 Configuration" { 17 18 register vendor_id rw addr( base, 0x00 ) "Vendor ID" type(uint16); 19 register device_id rw addr( base, 0x02 ) "Device ID" type(uint16); 20 21 register command rw addr( base, 0x04 ) "Command" { 22 _ 5; 23 int_dis 1 rw "Interrupt disable"; 24 back2back 1 ro "Fast back-to-back enable"; 25 serr 1 rw "SERR# enable"; 26 stepping 1 ro "IDSEL stepping/wait cycle control"; 27 parity 1 rw "Parity error response"; 28 vga_snoop 1 ro "VGA palette snoop enable"; 29 mem_inval 1 ro "Memory write and invalidate enable"; 30 special 1 ro "Special cycles"; 31 master 1 rw "Bus master"; 32 mem_space 1 rw "Memory space enable"; 33 io_space 1 rw "I/O space enable"; 34 }; 35 36 register status addr( base, 0x06 ) "Status" { 37 parity_err 1 rwc "Detected parity error"; 38 system_err 1 rwc "Signalled system error"; 39 rx_m_abrt 1 rwc "Received master abort"; 40 rx_t_abrt 1 rwc "Received target abort"; 41 sig_t_abrt 1 rwc "Signalled target abort"; 42 devsel 2 ro "DEVSEL timing"; 43 md_parity 1 rwc "Master data parity error"; 44 back2back 1 ro "Fast Back-to-Back enable"; 45 udf 1 ro "UDF supported"; 46 m66 1 ro "66MHz capable"; 47 caplist 1 ro "Capabilities list"; 48 intstat 1 ro "Interrupt status"; 49 _ 3; 50 }; 51 52 // 53 // Revision ID and Class code fall in the same 32-bit space. We 54 // allow access to the Revision ID as an 8-bit value, and the Class 55 // Code as a 32-bit value with the bottom 8 bits reserved, but we 56 // could I suppose combine them all into one register. 57 // 58 59 register rev_id ro addr( base, 0x08 ) "Revision ID" type(uint8); 60 61 constants classcode "Class code" { 62 old = 0x00 "Pre-2.0 PCI device"; 63 mass = 0x01 "Mass storage controller"; 64 network = 0x02 "Network controller"; 65 display = 0x03 "Display controller"; 66 multimedia = 0x04 "Multimedia device"; 67 memory = 0x05 "Memory controller"; 68 bridge = 0x06 "Bridge device"; 69 simple = 0x07 "Simple communications controller"; 70 base = 0x08 "Base system peripherals"; 71 input = 0x09 "Input device"; 72 docking = 0x0a "Docking station"; 73 processor = 0x0b "Processor"; 74 serial = 0x0c "Serial bus controller"; 75 wireless = 0x0d "Wireless controller"; 76 intelligent = 0x0e "Intelligent I/O controller"; 77 satellite = 0x0f "Satellite communications controller"; 78 crypt = 0x10 "Encryption/decryption device"; 79 acquisition = 0x11 "Data acquisition controller"; 80 misc = 0xff "Miscellaneous"; 81 }; 82 83 register class_code rw also addr( base, 0x08 ) "Class code" { 84 clss 8 type(classcode) "Class code"; 85 subclss 8 "Subclass code"; 86 prog_if 8 "Programming intf"; 87 _ 8; 88 }; 89 90 register cache_sz rw addr( base, 0x0c ) "Cache line size" type(uint8); 91 register latency rw addr( base, 0x0d ) "Master latency timer" type(uint8); 92 93 // 94 // Important stuff: whether this is actually a Type-0 header at 95 // all. This is currently duplicated into the Type-1 definition - 96 // when Mackerel gets a module system we can break this out into 97 // other files. 98 // 99 constants hdrtype "Configuration header types" { 100 nonbridge = 0 "non-bridge function"; 101 pci2pci = 1 "PCI-to-PCI bridge"; 102 cardbus = 2 "CardBus bridge"; 103 }; 104 105 register hdr_type ro addr( base, 0x0e ) "Header type" { 106 multi 1 "Multifunction device"; 107 fmt 7 type(hdrtype) "Configuration header format"; 108 }; 109 110 register bist addr( base, 0x0f ) "Built-in self-test" { 111 cap 1 ro "BIST capable"; 112 start 1 rw "Start BIST"; 113 _ 2; 114 comp 4 ro "Completion code"; 115 }; 116 117 // 118 // Base-Address registers. These are problematic for Mackerel, 119 // since you don't know exactly what the register is (32, 64, or IO) 120 // until you read it. And only then do you know where the next one 121 // might be. This is beyond Mackerel, and in all honesty probably 122 // should stay that way. 123 // 124 // As a compromise we define register types for each BAR, and give 125 // the BAR block as simply a set of 6 32-bit registers. PCI 126 // enumeration code can do the rest. 127 // 128 constants bardecoder "BAR decoder type" { 129 bar_32bit = 0b00 "32-bit decoder"; 130 bar_64bit = 0b10 "64-bit decoder"; 131 }; 132 133 regtype bar32 "32-bit memory base address" { 134 base 25 rw "Base address"; 135 _ 3; 136 prefetch 1 ro "Prefetchable"; 137 tpe 2 ro type(bardecoder) "Memory decoder type"; 138 space 1 ro "Memory space indicator"; 139 }; 140 regtype bar64 "64-bit memory base address" { 141 base 57 rw "Base address"; 142 _ 3; 143 prefetch 1 ro "Prefetchable"; 144 tpe 2 ro type(bardecoder) "Memory decoder type"; 145 space 1 ro "Memory space indicator"; 146 }; 147 regtype bario "I/O space base address" { 148 base 30 rw "Base address"; 149 _ 1; 150 space 1 ro "I/O space indicator"; 151 }; 152 153 regarray bars addr( base, 0x10 ) [5] "Base address registers" type(uint32); 154 155 register cardbus ro addr(base, 0x28) "CardBus CIS ptr" type(uint32); 156 157 register subsys_vid ro addr(base, 0x2c) "Subsystem vendor ID" type(uint16); 158 register subsys_id ro addr(base, 0x2e) "Subsystem ID" type(uint16); 159 160 register rom_base rw addr(base, 0x30) "Expansion ROM base addr" { 161 base 21 "ROM Base address high bits"; 162 _ 10; 163 enable 1 "ROM address decoder enable"; 164 }; 165 166 register cap_ptr ro addr(base, 0x34) "Capabilities ptr" type(uint8); 167 168 register int_line rw addr(base, 0x3c) "Interrupt line" type(uint8); 169 register int_pin ro addr(base, 0x3d) "Interrupt ping" type(uint8); 170 171 register min_gnt ro addr(base, 0x3e) "Min Gnt" type(uint8); 172 register max_lat ro addr(base, 0x3f) "Max Lat" type(uint8); 173 174}; 175 176 177