1/* 2 * Copyright (c) 2018, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * pci_e1000_msix_cap.dev 11 * 12 * DESCRIPTION: PCI E1000 MSI-X Capability. The e1k uses a non-standard 13 * PCI capabality to describe the MSI-X functionality. 14 * 15 * Source: Intel 82574L GBE Controller Familiy Datasheet 16 */ 17 18device pci_e1000_msix_cap lsbfirst ( addr base ) "PCI E1000 MSI-X Capability" { 19 20 // 9.1.5 21 register hdr rw addr(base, 0x00 ) "Capabilities Header" { 22 id 8 "Capability ID"; 23 next 8 "Next Pointer"; 24 tblsize 11 "Message Control - Table Size"; 25 _ 3 mbz; 26 fm 1 "Function Mask"; 27 en 1 "MSI-X Enable"; 28 }; 29 30 register msg_upper_addr rw addr(base, 0x04) "Message Upper Address" type(uint32); 31 32 register tbl_location ro addr(base, 0x08) "MSI-X Table Location" { 33 bir 3 "Base Address Register Index"; 34 offset 29 "Table offset"; 35 }; 36 37}; 38