1/*
2 * Copyright (c) 2012, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * omap44xx_id.dev
11 *
12 * DESCRIPTION: OMAP44xx device identification
13 *
14 * This is derived from:
15 *
16 * OMAP4430 Multimedia Device Silicon Revision 2.x Technical Reference
17 * Manual Version O 
18 * OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
19 * Manual Version Q
20 * 
21 * Section numbers are from the latter. 
22 *
23 */
24
25device omap44xx_usbconf msbfirst ( addr base ) "OMAP44xx USB host subsystem" {
26
27    // 23.11.6.2.2
28
29    register revision ro addr(base, 0x0000) "Revision"
30	type(uint32);
31
32    register hwinfo ro addr(base, 0x0004) "Hardware info" {
33	_		24;
34	sar_cntx_size	8	"Save-and-Restore context size";
35    };
36
37
38    constants idle_mode width(2) "Slave interface power mode" {
39	idle_force = 0b00	"Force-Idle mode";
40	idle_no	   = 0b01	"No idle mode";
41	idle_smart = 0b10	"Smart-idle mode";
42    };	
43
44    register config rw addr(base, 0x0010) "Module configuration" {
45	_		23;
46	clock_act	1	"Enable autogating OCP-derived int. clks.";
47        _		3;
48	s_idle_mode	2 type(idle_mode) "Slave intf. power mgmt. ctrl";
49	ena_wakeup	1	"Asynchronous wake-up generation control";
50	soft_reset	1 wo	"Module software reset";
51	auto_idle	1	"Internal autogating control";
52    };
53
54    register status ro addr(base, 0x0014) "Module status" {
55	_		31;
56	reset_done	1	"Module has entirely come out of reset";
57    };
58
59    register irqstat rw1c addr(base, 0x0018) "IRQ status" {
60	_		29 rsvd;
61	access_error	1 	"Access error to ULPI register over OCP";
62	fclk_end	1	"Functional clock no longer requested";
63	fclk_start	1	"Functional clock requested for USB clocking";
64    };
65
66    register irqenable rw addr(base, 0x001c) "IRQ enable" {
67	_		29 rsvd;
68	access_error	1 	"Access error to ULPI register over OCP";
69	fclk_end	1	"Functional clock no longer requested";
70	fclk_start	1	"Functional clock requested for USB clocking";
71    };
72
73    register shared_conf rw addr(base, 0x0030) "Shared configuration" {
74	_		30 rsvd;
75	fclk_req	1	"Functional clock request";
76	fclk_is_on	1	"Status of the functional clock input";
77    };
78
79    constants line_state width(2) "Line state" {
80	se0 = 0b00	"Single-ended 0";
81	fsj = 0b01	"Full-Speed J = differential 1";
82	fsk = 0b10	"Full-Speed K = differential 0";
83	se1 = 0b11	"Single-ended 1 (illegal in USB)";
84    };
85
86    constants si_mode width(4) "Serial interface mode" {
87	si_u6ps = 0x0	"6-pin unidirectional PHY i/f. Tx encoding Dat/Se0";
88	si_u6pd = 0x1	"6-pin unidirectional PHY i/f. Tx encoding is Dp/Dm";
89	si_b3p	= 0x2   "3-pin bidirectional PHY i/f";
90	si_b4p  = 0x3	"4-pin bidirectional PHY i/f";
91	si_u6ts = 0x4	"6-pin unidirectional TLL. Tx encoding is Dat/Se0";
92	si_u6td = 0x5	"6-pin unidirectional TLL. Tx encoding is Dp/Dm";
93	si_b3t	= 0x6	"3-pin bidirectional TLL";
94	si_b4t  = 0x7	"4-pin bidirectional TLL";
95	si_b2ts	= 0xa	"2-pin bidirectional TLL. Encoding is Dat/Se0";
96	si_b2td = 0xb	"2-pin bidirectional TLL. Encoding is Dp/Dm";
97    };
98	
99    constants ch_mode width(2) "Main channel mode" {
100	ch_u2u	= 0b00	"UTMI-to-ULPI TLL mode (HS capable)";
101	ch_u2s  = 0b01  "UTMI-to-serial (FS/LS)";
102	ch_trans= 0b10	"Transparent UTMI mode: to UTMI PHY";
103	ch_none = 0b11	"No mode selected";
104    };
105
106    regarray channel_conf rw addr(base, 0x0040)[2] "Channel configuration" {
107	_		2 rsvd;
108	fslslinestate	2 type(line_state) "Line state for serial modes";
109	fslsmode	4 type(si_mode)	"Serial interface mode select";
110	_		3 rsvd;
111	testtxse0	1	"Force-Se0 tx override for mode test";
112	testtxdat	1	"Differential data tx override for mode test";
113	testtxen	1	"Differential data tx override for mode test";
114	testen		1	"Enable manual test override for Tx path";
115	drvvbus		1	"VBUS-drive for ChanMode = serial";
116	chrgvbus	1	"VBUS-charge for ChanMode = serial";
117	_		3 rsvd;
118	ulpinobitstuff	1	"Disable bitstuff emulation in ULPI TLL";
119	ulpiautoidle	1	"Allow ULPI output clock to idle";
120	utmiautoidle	1	"Allow UTMI clock to idle";
121	_		1 rsvd;
122	ulpioutclkmode	1 ro	"ULPI clocking mode select";
123	tllfullspeed	1	"PHY speed emul. in TLL (full/slow)";
124	tllconnect	1	"Emulate Full/Low-Speed connect";
125	tllattach	1	"Emulate cable attach/detach";
126	utmiisadev	1	"Select cable end seen by UTMI side of TLL";
127	chanmode	2	"Main channel mode selection";
128	chanen		1	"Active-high channel enable";
129    };
130
131    regarray sar_cntx rw addr(base, 0x0400)[7] 
132	"Save and restore context array" 
133	type(uint32);
134};
135