1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_sysctrl_icont.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_sysctrl_icont msbfirst ( addr base ) "" { 29 30 31 register ivahd_revision ro addr(base, 0x0) "IP revision identifier (X.Y.R). Used by software to track features, bugs, and compatibility" type(uint32); 32 33 constants sl2bank_status width(2) "" { 34 SL2BANK_0_r = 0 "1 memory bank"; 35 SL2BANK_1_r = 1 "2 memory bank"; 36 SL2BANK_2_r = 2 "4 memory bank"; 37 SL2BANK_3_r = 3 "8 memory bank"; 38 }; 39 40 constants sl2size_status width(4) "" { 41 SL2SIZE_1_r = 1 "16KB"; 42 SL2SIZE_2_r = 2 "32KB"; 43 SL2SIZE_3_r = 3 "48KB"; 44 SL2SIZE_4_r = 4 "64KB"; 45 SL2SIZE_5_r = 5 "96KB"; 46 SL2SIZE_6_r = 6 "128KB"; 47 SL2SIZE_7_r = 7 "160KB"; 48 SL2SIZE_8_r = 8 "192KB"; 49 SL2SIZE_9_r = 9 "224KB"; 50 SL2SIZE_10_r = 10 "256KB"; 51 SL2SIZE_11_r = 11 "320KB"; 52 SL2SIZE_12_r = 12 "384KB"; 53 SL2SIZE_13_r = 13 "448KB"; 54 SL2SIZE_14_r = 14 "512KB"; 55 }; 56 57 register ivahd_hwinfo addr(base, 0x4) "Information about the IP module's hardware configuration." { 58 _ 17 mbz; 59 ecd3 1 ro "ECD3 available 0: ECD3 not present 1: ECD3 present"; 60 mc3 1 ro "MC3 available 0: MC3 not present 1: MC3 present"; 61 ipe3 1 ro "iPE3 available 0: iPE3 not present 1: iPE3 present"; 62 calc3 1 ro "CALC3 available 0: CALC3 not present 1: CALC3 present"; 63 ime3 1 ro "iME3 available 0: iME3 not present 1: iME3 present"; 64 ilf3 1 ro "iLF3 available 0: iLF3 not present 1: iLF3 present"; 65 vdma 1 ro "vDMA available 0: vDMA not present 1: vDMA present"; 66 icont2 1 ro "iCONT2 available 0: iCONT2 not present 1: iCONT2 present"; 67 icont1 1 ro "iCONT1 available 0: iCONT1 not present 1: iCONT1 present"; 68 sl2bank 2 ro type(sl2bank_status) ""; 69 sl2size 4 ro type(sl2size_status) "Size of SL2 memory"; 70 }; 71 72 constants standbymode_status width(2) "" { 73 STANDBYMODE_1 = 1 "No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only."; 74 STANDBYMODE_2 = 2 "Smart-standby mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator. IP module shall not generate (initiator-related) wakeup events."; 75 }; 76 77 constants idlemode_status width(2) "" { 78 IDLEMODE_1 = 1 "No-idle mode: local target never enters idle state. Backup mode, for debug only."; 79 IDLEMODE_2 = 2 "Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events."; 80 }; 81 82 register ivahd_sysconfig addr(base, 0x10) "Clock management configuration" { 83 _ 26 mbz; 84 standbymode 2 rw type(standbymode_status) "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state.0x0 and 0x3: Reserved ."; 85 idlemode 2 rw type(idlemode_status) "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state.0x0 and 0x3: Reserved ."; 86 _ 2 mbz; 87 }; 88 89 constants sysctrl_clkerr_status width(1) "" { 90 SYSCTRL_CLKERR_0_w = 0 "No action"; 91 SYSCTRL_CLKERR_0_r = 0 "No event pending"; 92 SYSCTRL_CLKERR_1_r = 1 "Event pending"; 93 SYSCTRL_CLKERR_1_w = 1 "Set event (debug)"; 94 }; 95 96 register ivahd_irqstatus_raw addr(base, 0x24) "Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 97 _ 31 mbz; 98 sysctrl_clkerr 1 rw type(sysctrl_clkerr_status) "Settable raw status for Clock Programming Error event"; 99 }; 100 101 constants sysctrl_clkerr_status1 width(1) "" { 102 SYSCTRL_CLKERR_0_w_1 = 0 "No action"; 103 SYSCTRL_CLKERR_0_r_1 = 0 "No (enabled) event pending"; 104 SYSCTRL_CLKERR_1_r_1 = 1 "Event pending"; 105 SYSCTRL_CLKERR_1_w_1 = 1 "Clear (raw) event"; 106 }; 107 108 register ivahd_irqstatus addr(base, 0x28) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 109 _ 31 mbz; 110 sysctrl_clkerr 1 rw type(sysctrl_clkerr_status1) "Clearable, enabled status for Clock Programming Error event"; 111 }; 112 113 constants sysctrl_clkerr_status2 width(1) "" { 114 SYSCTRL_CLKERR_0_w_2 = 0 "No action"; 115 SYSCTRL_CLKERR_0_r_2 = 0 "Interrupt disabled (masked)"; 116 SYSCTRL_CLKERR_1_r_2 = 1 "Interrupt enabled"; 117 SYSCTRL_CLKERR_1_w_2 = 1 "Enable interrupt"; 118 }; 119 120 register ivahd_irqenable_set addr(base, 0x2C) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 121 _ 31 mbz; 122 sysctrl_clkerr 1 rw type(sysctrl_clkerr_status2) "Clock Programing Error"; 123 }; 124 125 constants sysctrl_clkerr_status3 width(1) "" { 126 SYSCTRL_CLKERR_0_w_3 = 0 "No action"; 127 SYSCTRL_CLKERR_0_r_3 = 0 "Interrupt disabled (masked)"; 128 SYSCTRL_CLKERR_1_r_3 = 1 "Interrupt enabled"; 129 SYSCTRL_CLKERR_1_w_3 = 1 "Disable interrupt"; 130 }; 131 132 register ivahd_irqenable_clr addr(base, 0x30) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 133 _ 31 mbz; 134 sysctrl_clkerr 1 rw type(sysctrl_clkerr_status3) "Clock Programing Error"; 135 }; 136 137 register ivahd_sync_irqstatus_raw addr(base, 0x34) "Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 138 _ 24 mbz; 139 sync_input7_0 8 rw "Settable raw status for SYNC INPUT event. For each bit of the bit field: Read 0: No event pending Read 1: Event pending Write 0: No action Write 1: Set event (debug)"; 140 }; 141 142 register ivahd_sync_irqstatus addr(base, 0x38) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 143 _ 24 mbz; 144 sync_input7_0 8 rw "Clearable, enabled status for SYNC INPUT event. For each bit of the bit field: Read 0: No (enabled) event pending Read 1: Event pending Write 0: No action Write 1: Clear (raw) event"; 145 }; 146 147 register ivahd_sync_irqenable_set addr(base, 0x3C) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 148 _ 24 mbz; 149 sync_input7_0 8 rw "Enable for interrupt event. For each bit of the bit field: Read 0: Interrupt disabled (masked) Read 1: Interrupt enabled Write 0: No action Write 1: Enable interrupt"; 150 }; 151 152 register ivahd_sync_irqenable_clr addr(base, 0x40) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 153 _ 24 mbz; 154 sync_input7_0 8 rw "Enable for interrupt event. For each bit of the bitfiled: Read 0: Interrupt disabled (masked) Read 1: Interrupt enabled Write 0: No action Write 1: Disable interrupt"; 155 }; 156 157 register ivahd_clkctrl addr(base, 0x50) "IVA-HD clock control register" { 158 _ 21 mbz; 159 smset 1 rw "Clock control of SMSET 0: Exit idle state and start SMSET clock 1: Request SMSET to go to idle state and stop SMSET clock Note: Shutting down SMSET clock may hang system if software performs software instrumentation and/or access to its configuration port."; 160 msgif 1 rw "Clock control of MSGIF 0: Exit idle state and start MSGIF clock 1: Request MSGIF to go to idle state and stop MSGIF clock"; 161 ecd3 1 rw "Clock control of ECD3 0: Exit idle state and start ECD3 clock 1: Request ECD3 to go to idle state and stop ECD3 clock"; 162 mc3 1 rw "Clock control of MC3 0: Exit idle state and start MC3 clock 1: Request MC3 to go to idle state and stop MC3 clock"; 163 ipe3 1 rw "Clock control of iPE3 0: Exit idle state and start iPE3 clock 1: Request iME3 to go to idle state and stop iPE3 clock"; 164 calc3 1 rw "Clock control of CALC3 0: Exit idle state and start CALC3 clock 1: Request CALC3 to go to idle state and stop CALC3 clock"; 165 ilf3 1 rw "Clock control of iLF3 0: Exit idle state and start iLF3 clock 1: Request iLF3 to go to idle state and stop iLF3 clock"; 166 ime3 1 rw "Clock control of iME3 0: Exit idle state and start iME3 clock 1: Request iME3 to go to idle state and stop iME3 clock"; 167 vdma 1 rw "Clock control of vDMA 0: Exit idle state and start vDMA clock 1: Request vDMA to go to idle state and stop vDMA clock"; 168 icont2 1 rw "Clock control of iCONT2 0: Exit idle state and start iCONT2 clock 1: Request iCONT2 to go to idle state and stop iCONT2 clock"; 169 icont1 1 rw "Clock control of iCONT1 0: Exit idle state and start iCONT1 clock 1: Request iCONT1 to go to idle state and stop iCONT1 clock"; 170 }; 171 172 register ivahd_clkst addr(base, 0x54) "IVA-HD clock status register" { 173 _ 21 mbz; 174 smset 1 ro "Clock status of SMSET 1: SMSET clock is active 0: SMSET clock is idled"; 175 msgif 1 ro "Clock status of MSGIF 1: MSGIF clock is active 0: MSGIF clock is idled"; 176 ecd3 1 ro "Clock status of ECD3 1: ECD3 clock is active 0: ECD3 clock is idled"; 177 mc3 1 ro "Clock status of MC3 1: MC3 clock is active 0: MC3 clock is idled"; 178 ipe3 1 ro "Clock status of iPE3 1: iPE3 clock is active 0: iPE3 clock is idled"; 179 calc3 1 ro "Clock status of CALC3 1: CALC3 clock is active 0: CALC3 clock is idled"; 180 ilf3 1 ro "Clock status of iLF3 1: iLF3 clock is active 0: iLF3 clock is idled"; 181 ime3 1 ro "Clock status of iME3 1: iME3 clock is active 0: iME3 clock is idled"; 182 vdma 1 ro "Clock status of vDMA 1: vDMA clock is active 0: vDMA clock is idled"; 183 icont2 1 ro "Clock status of iCONT2 1: iCONT2 clock is active 0: iCONT2 clock is idled"; 184 icont1 1 ro "Clock status of iCONT1 1: iCONT1 clock is active 0: iCONT1 clock is idled"; 185 }; 186 187 register ivahd_stdbyst addr(base, 0x58) "IVA-HD STANDBY status" { 188 _ 29 mbz; 189 vdma 1 ro "vDMA Standby status 0: module is not in Standby 1: module is in Standby"; 190 icont2 1 ro "iCONT2 Standby status 0: module is not in Standby 1: module is in Standby"; 191 icont1 1 ro "iCONT1 Standby status 0: module is not in Standby 1: module is in Standby"; 192 }; 193};