1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_simcop_control_l3interconnect.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_simcop_control_l3interconnect msbfirst ( addr base ) "" { 29 30 31 register simcop_hl_revision ro addr(base, 0x0) "MODULE REVISION This register contains the IP revision code in binary coded digital. For example, we have: 0x01 = revision 0.1 and 0x21 = revision 2.1" type(uint32); 32 33 constants ldcr_resp_fifo_status width(3) "" { 34 LDCR_RESP_FIFO_2_r = 2 "8x128 bits"; 35 LDCR_RESP_FIFO_3_r = 3 "16x128 bits"; 36 LDCR_RESP_FIFO_4_r = 4 "32x128 bits"; 37 LDCR_RESP_FIFO_5_r = 5 "64x128 bits"; 38 LDCR_RESP_FIFO_6_r = 6 "128x128 bits"; 39 LDCR_RESP_FIFO_7_r = 7 "256x256 bits"; 40 }; 41 42 constants image_buffers_status width(2) "" { 43 IMAGE_BUFFERS_0_r = 0 "4 Image buffers (e, f, g, h)"; 44 IMAGE_BUFFERS_1_r = 1 "8 Image buffers"; 45 }; 46 47 constants rot_a_enable_status width(1) "" { 48 ROT_A_ENABLE_0_r = 0 "Disabled at design time"; 49 ROT_A_ENABLE_1_r = 1 "Enabled at design time"; 50 }; 51 52 register simcop_hl_hwinfo addr(base, 0x4) "Information about the IP module's hardware configuration. It provides information about the generic parameters." { 53 _ 19 mbz; 54 ldcr_resp_fifo 3 ro type(ldcr_resp_fifo_status) "Defines the size of the LDC read master response FIFO in words of 128-bits."; 55 image_buffers 2 ro type(image_buffers_status) "This parameter defines the image buffer count."; 56 _ 1 mbz; 57 rot_a_enable 1 ro type(rot_a_enable_status) "The ROT a is present when this parameter is set."; 58 imx_b_enable 1 ro type(rot_a_enable_status) "The iMX B module and the CMD b, COEFF b memories are present when this parameter is set."; 59 imx_a_enable 1 ro type(rot_a_enable_status) "The iMX A module and the CMD a, COEFF a memories are present when this parameter is set."; 60 nsf_enable 1 ro type(rot_a_enable_status) "The NSF2 is present when this parameter is set."; 61 vlcdj_enable 1 ro type(rot_a_enable_status) "The VLCD module and the QUANT, HUFFMAN, BITSTREAM memories are present when this parameter is set."; 62 dct_enable 1 ro type(rot_a_enable_status) "The DCT module is present when this parameter is set."; 63 ldc_enable 1 ro type(rot_a_enable_status) "The LDC module and the LDC LUT are present when this parameter is set."; 64 }; 65 66 constants standbymode_status width(2) "" { 67 STANDBYMODE_0 = 0 "Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only."; 68 STANDBYMODE_1 = 1 "No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only."; 69 STANDBYMODE_2 = 2 "Smart-standby mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator."; 70 }; 71 72 constants softreset_status width(1) "" { 73 SOFTRESET_0_r = 0 "Reset done, no pending action"; 74 SOFTRESET_0_w = 0 "No action"; 75 SOFTRESET_1_w = 1 "Initiate software reset"; 76 SOFTRESET_1_r = 1 "Reset (software or other) ongoing"; 77 }; 78 79 register simcop_hl_sysconfig addr(base, 0x10) "This register controls the various parameters of the OCP interface" { 80 _ 26 mbz; 81 standbymode 2 rw type(standbymode_status) "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state."; 82 _ 3 mbz; 83 softreset 1 rw type(softreset_status) "Software reset"; 84 }; 85 86 constants cpu_proc_start_irq_status width(1) "" { 87 CPU_PROC_START_IRQ_0_w = 0 "No action"; 88 CPU_PROC_START_IRQ_0_r = 0 "No event pending"; 89 CPU_PROC_START_IRQ_1_r = 1 "Event pending"; 90 CPU_PROC_START_IRQ_1_w = 1 "Set event (debug)"; 91 }; 92 93 register simcop_hl_irqstatus_raw_i_0 addr(base, 0x20) "Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 94 _ 12 mbz; 95 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 96 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 97 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status) "The LDC2 bridge has generated an error."; 98 icnt_err_irq 1 rw type(cpu_proc_start_irq_status) "An error has been received on the SIMCOP master port."; 99 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status) "A decode error has been signaled by the VLCDJ module"; 100 done_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received."; 101 step3_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 3 is activated by the hardware sequencer"; 102 step2_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 2 is activated by the hardware sequencer"; 103 step1_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 1 is activated by the hardware sequencer"; 104 step0_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 0 is activated by the hardware sequencer"; 105 ldc_block_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a macroblock has been processed"; 106 _ 1 mbz; 107 rot_a 1 rw type(cpu_proc_start_irq_status) "Event triggered by the ROT a engine"; 108 imx_b_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 109 imx_a_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 110 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 111 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 112 dct_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 113 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a full frame has been processed"; 114 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 115 }; 116 117 register simcop_hl_irqstatus_raw_i_1 addr(base, 0x30) "Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 118 _ 12 mbz; 119 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 120 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 121 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status) "The LDC2 bridge has generated an error."; 122 icnt_err_irq 1 rw type(cpu_proc_start_irq_status) "An error has been received on the SIMCOP master port."; 123 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status) "A decode error has been signaled by the VLCDJ module"; 124 done_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received."; 125 step3_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 3 is activated by the hardware sequencer"; 126 step2_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 2 is activated by the hardware sequencer"; 127 step1_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 1 is activated by the hardware sequencer"; 128 step0_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 0 is activated by the hardware sequencer"; 129 ldc_block_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a macroblock has been processed"; 130 _ 1 mbz; 131 rot_a 1 rw type(cpu_proc_start_irq_status) "Event triggered by the ROT a engine"; 132 imx_b_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 133 imx_a_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 134 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 135 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 136 dct_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 137 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a full frame has been processed"; 138 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 139 }; 140 141 register simcop_hl_irqstatus_raw_i_2 addr(base, 0x40) "Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 142 _ 12 mbz; 143 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 144 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 145 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status) "The LDC2 bridge has generated an error."; 146 icnt_err_irq 1 rw type(cpu_proc_start_irq_status) "An error has been received on the SIMCOP master port."; 147 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status) "A decode error has been signaled by the VLCDJ module"; 148 done_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received."; 149 step3_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 3 is activated by the hardware sequencer"; 150 step2_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 2 is activated by the hardware sequencer"; 151 step1_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 1 is activated by the hardware sequencer"; 152 step0_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 0 is activated by the hardware sequencer"; 153 ldc_block_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a macroblock has been processed"; 154 _ 1 mbz; 155 rot_a 1 rw type(cpu_proc_start_irq_status) "Event triggered by the ROT a engine"; 156 imx_b_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 157 imx_a_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 158 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 159 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 160 dct_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 161 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a full frame has been processed"; 162 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 163 }; 164 165 register simcop_hl_irqstatus_raw_i_3 addr(base, 0x50) "Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 166 _ 12 mbz; 167 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 168 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 169 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status) "The LDC2 bridge has generated an error."; 170 icnt_err_irq 1 rw type(cpu_proc_start_irq_status) "An error has been received on the SIMCOP master port."; 171 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status) "A decode error has been signaled by the VLCDJ module"; 172 done_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when the hardware sequencer finishes the sequence: - the sequence step counter has reached the limit - all accelerator and DMA events for the last sequence step have been received."; 173 step3_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 3 is activated by the hardware sequencer"; 174 step2_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 2 is activated by the hardware sequencer"; 175 step1_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 1 is activated by the hardware sequencer"; 176 step0_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when Step 0 is activated by the hardware sequencer"; 177 ldc_block_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a macroblock has been processed"; 178 _ 1 mbz; 179 rot_a 1 rw type(cpu_proc_start_irq_status) "Event triggered by the ROT a engine"; 180 imx_b_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 181 imx_a_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when iMX has executed a SLEEP instruction."; 182 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 183 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 184 dct_irq 1 rw type(cpu_proc_start_irq_status) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 185 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status) "This event is triggered by LDC when a full frame has been processed"; 186 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 187 }; 188 189 constants cpu_proc_start_irq_status1 width(1) "" { 190 CPU_PROC_START_IRQ_0_w_4 = 0 "No action"; 191 CPU_PROC_START_IRQ_0_r_4 = 0 "No (enabled) event pending"; 192 CPU_PROC_START_IRQ_1_r_4 = 1 "Event pending"; 193 CPU_PROC_START_IRQ_1_w_4 = 1 "Clear (raw) event"; 194 }; 195 196 register simcop_hl_irqstatus_i_0 addr(base, 0x24) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 197 _ 12 mbz; 198 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 199 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 200 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "The LDC2 bridge has generated an error."; 201 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "An error has been received on the SIMCOP master port."; 202 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "A decode error has been signaled by the VLCDJ module"; 203 done_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 204 step3_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 3 is activated by the hardware sequencer"; 205 step2_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 2 is activated by the hardware sequencer"; 206 step1_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 1 is activated by the hardware sequencer"; 207 step0_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 0 is activated by the hardware sequencer"; 208 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a macroblock has been processed"; 209 _ 1 mbz; 210 rot_a 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the ROT a engine"; 211 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 212 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 213 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 214 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 215 dct_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 216 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a full frame has been processed"; 217 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 218 }; 219 220 register simcop_hl_irqstatus_i_1 addr(base, 0x34) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 221 _ 12 mbz; 222 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 223 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 224 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "The LDC2 bridge has generated an error."; 225 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "An error has been received on the SIMCOP master port."; 226 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "A decode error has been signaled by the VLCDJ module"; 227 done_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 228 step3_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 3 is activated by the hardware sequencer"; 229 step2_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 2 is activated by the hardware sequencer"; 230 step1_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 1 is activated by the hardware sequencer"; 231 step0_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 0 is activated by the hardware sequencer"; 232 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a macroblock has been processed"; 233 _ 1 mbz; 234 rot_a 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the ROT a engine"; 235 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 236 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 237 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 238 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 239 dct_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 240 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a full frame has been processed"; 241 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 242 }; 243 244 register simcop_hl_irqstatus_i_2 addr(base, 0x44) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 245 _ 12 mbz; 246 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 247 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 248 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "The LDC2 bridge has generated an error."; 249 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "An error has been received on the SIMCOP master port."; 250 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "A decode error has been signaled by the VLCDJ module"; 251 done_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 252 step3_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 3 is activated by the hardware sequencer"; 253 step2_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 2 is activated by the hardware sequencer"; 254 step1_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 1 is activated by the hardware sequencer"; 255 step0_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 0 is activated by the hardware sequencer"; 256 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a macroblock has been processed"; 257 _ 1 mbz; 258 rot_a 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the ROT a engine"; 259 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 260 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 261 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 262 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 263 dct_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 264 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a full frame has been processed"; 265 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 266 }; 267 268 register simcop_hl_irqstatus_i_3 addr(base, 0x54) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 269 _ 12 mbz; 270 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 271 simcop_dma_irq1 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 272 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "The LDC2 bridge has generated an error."; 273 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "An error has been received on the SIMCOP master port."; 274 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status1) "A decode error has been signaled by the VLCDJ module"; 275 done_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when the hardware sequencer finishes the sequence: -The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 276 step3_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 3 is activated by the hardware sequencer"; 277 step2_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 2 is activated by the hardware sequencer"; 278 step1_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 1 is activated by the hardware sequencer"; 279 step0_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when Step 0 is activated by the hardware sequencer"; 280 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a macroblock has been processed"; 281 _ 1 mbz; 282 rot_a 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the ROT a engine"; 283 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 284 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when iMX has executed a SLEEP instruction."; 285 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 286 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 287 dct_irq 1 rw1c type(cpu_proc_start_irq_status1) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 288 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status1) "This event is triggered by LDC when a full frame has been processed"; 289 simcop_dma_irq0 1 ro type(cpu_proc_start_irq_status1) "Event triggered by the SIMCOP DMA. This event is automatically cleared at SIMCOP level when it is cleared at SIMCOP DMA level. Check SIMCOP DMA IRQ registers."; 290 }; 291 292 constants cpu_proc_start_irq_status2 width(1) "" { 293 CPU_PROC_START_IRQ_0_w_8 = 0 "No action"; 294 CPU_PROC_START_IRQ_0_r_8 = 0 "Interrupt disabled (masked)"; 295 CPU_PROC_START_IRQ_1_r_8 = 1 "Interrupt enabled"; 296 CPU_PROC_START_IRQ_1_w_8 = 1 "Enable interrupt"; 297 }; 298 299 register simcop_hl_irqenable_set_i_0 addr(base, 0x28) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 300 _ 12 mbz; 301 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 302 simcop_dma_irq1 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 303 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status2) "The LDC2 bridge has generated an error."; 304 icnt_err_irq 1 rw type(cpu_proc_start_irq_status2) "An error has been received on the SIMCOP master port."; 305 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status2) "A decode error has been signaled by the VLCDJ module"; 306 done_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 307 step3_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 3 is activated by the hardware sequencer"; 308 step2_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 2 is activated by the hardware sequencer"; 309 step1_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 1 is activated by the hardware sequencer"; 310 step0_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 0 is activated by the hardware sequencer"; 311 ldc_block_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a macroblock has been processed"; 312 _ 1 mbz; 313 rot_a 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the ROT a engine"; 314 imx_b_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 315 imx_a_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 316 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 317 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 318 dct_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 319 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a full frame has been processed"; 320 simcop_dma_irq0 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 321 }; 322 323 register simcop_hl_irqenable_set_i_1 addr(base, 0x38) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 324 _ 12 mbz; 325 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 326 simcop_dma_irq1 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 327 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status2) "The LDC2 bridge has generated an error."; 328 icnt_err_irq 1 rw type(cpu_proc_start_irq_status2) "An error has been received on the SIMCOP master port."; 329 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status2) "A decode error has been signaled by the VLCDJ module"; 330 done_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 331 step3_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 3 is activated by the hardware sequencer"; 332 step2_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 2 is activated by the hardware sequencer"; 333 step1_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 1 is activated by the hardware sequencer"; 334 step0_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 0 is activated by the hardware sequencer"; 335 ldc_block_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a macroblock has been processed"; 336 _ 1 mbz; 337 rot_a 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the ROT a engine"; 338 imx_b_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 339 imx_a_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 340 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 341 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 342 dct_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 343 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a full frame has been processed"; 344 simcop_dma_irq0 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 345 }; 346 347 register simcop_hl_irqenable_set_i_2 addr(base, 0x48) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 348 _ 12 mbz; 349 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 350 simcop_dma_irq1 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 351 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status2) "The LDC2 bridge has generated an error."; 352 icnt_err_irq 1 rw type(cpu_proc_start_irq_status2) "An error has been received on the SIMCOP master port."; 353 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status2) "A decode error has been signaled by the VLCDJ module"; 354 done_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 355 step3_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 3 is activated by the hardware sequencer"; 356 step2_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 2 is activated by the hardware sequencer"; 357 step1_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 1 is activated by the hardware sequencer"; 358 step0_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 0 is activated by the hardware sequencer"; 359 ldc_block_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a macroblock has been processed"; 360 _ 1 mbz; 361 rot_a 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the ROT a engine"; 362 imx_b_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 363 imx_a_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 364 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 365 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 366 dct_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 367 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a full frame has been processed"; 368 simcop_dma_irq0 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 369 }; 370 371 register simcop_hl_irqenable_set_i_3 addr(base, 0x58) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 372 _ 12 mbz; 373 cpu_proc_start_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 374 simcop_dma_irq1 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 375 ldc2bridge_err_irq 1 rw type(cpu_proc_start_irq_status2) "The LDC2 bridge has generated an error."; 376 icnt_err_irq 1 rw type(cpu_proc_start_irq_status2) "An error has been received on the SIMCOP master port."; 377 vlcdj_decode_err_irq 1 rw type(cpu_proc_start_irq_status2) "A decode error has been signaled by the VLCDJ module"; 378 done_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 379 step3_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 3 is activated by the hardware sequencer"; 380 step2_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 2 is activated by the hardware sequencer"; 381 step1_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 1 is activated by the hardware sequencer"; 382 step0_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when Step 0 is activated by the hardware sequencer"; 383 ldc_block_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a macroblock has been processed"; 384 _ 1 mbz; 385 rot_a 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the ROT a engine"; 386 imx_b_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 387 imx_a_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when iMX has executed a SLEEP instruction."; 388 nsf_irq_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 389 vlcdj_bloc_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 390 dct_irq 1 rw type(cpu_proc_start_irq_status2) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 391 ldc_frame_irq 1 rw type(cpu_proc_start_irq_status2) "This event is triggered by LDC when a full frame has been processed"; 392 simcop_dma_irq0 1 rw type(cpu_proc_start_irq_status2) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 393 }; 394 395 constants cpu_proc_start_irq_status3 width(1) "" { 396 CPU_PROC_START_IRQ_0_w_12 = 0 "No action"; 397 CPU_PROC_START_IRQ_0_r_12 = 0 "Interrupt disabled (masked)"; 398 CPU_PROC_START_IRQ_1_r_12 = 1 "Interrupt enabled"; 399 CPU_PROC_START_IRQ_1_w_12 = 1 "Disable interrupt"; 400 }; 401 402 register simcop_hl_irqenable_clr_i_0 addr(base, 0x2C) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 403 _ 12 mbz; 404 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 405 simcop_dma_irq1 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 406 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "The LDC2 bridge has generated an error."; 407 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "An error has been received on the SIMCOP master port."; 408 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "A decode error has been signaled by the VLCDJ module"; 409 done_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 410 step3_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 3 is activated by the hardware sequencer"; 411 step2_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 2 is activated by the hardware sequencer"; 412 step1_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 1 is activated by the hardware sequencer"; 413 step0_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 0 is activated by the hardware sequencer"; 414 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a macroblock has been processed"; 415 _ 1 mbz; 416 rot_a 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the ROT a engine"; 417 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 418 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 419 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 420 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 421 dct_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 422 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a full frame has been processed"; 423 simcop_dma_irq0 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 424 }; 425 426 register simcop_hl_irqenable_clr_i_1 addr(base, 0x3C) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 427 _ 12 mbz; 428 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 429 simcop_dma_irq1 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 430 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "The LDC2 bridge has generated an error."; 431 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "An error has been received on the SIMCOP master port."; 432 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "A decode error has been signaled by the VLCDJ module"; 433 done_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 434 step3_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 3 is activated by the hardware sequencer"; 435 step2_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 2 is activated by the hardware sequencer"; 436 step1_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 1 is activated by the hardware sequencer"; 437 step0_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 0 is activated by the hardware sequencer"; 438 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a macroblock has been processed"; 439 _ 1 mbz; 440 rot_a 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the ROT a engine"; 441 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 442 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 443 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 444 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 445 dct_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 446 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a full frame has been processed"; 447 simcop_dma_irq0 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 448 }; 449 450 register simcop_hl_irqenable_clr_i_2 addr(base, 0x4C) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 451 _ 12 mbz; 452 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 453 simcop_dma_irq1 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 454 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "The LDC2 bridge has generated an error."; 455 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "An error has been received on the SIMCOP master port."; 456 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "A decode error has been signaled by the VLCDJ module"; 457 done_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 458 step3_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 3 is activated by the hardware sequencer"; 459 step2_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 2 is activated by the hardware sequencer"; 460 step1_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 1 is activated by the hardware sequencer"; 461 step0_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 0 is activated by the hardware sequencer"; 462 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a macroblock has been processed"; 463 _ 1 mbz; 464 rot_a 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the ROT a engine"; 465 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 466 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 467 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 468 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 469 dct_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 470 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a full frame has been processed"; 471 simcop_dma_irq0 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 472 }; 473 474 register simcop_hl_irqenable_clr_i_3 addr(base, 0x5C) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 475 _ 12 mbz; 476 cpu_proc_start_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the hardware sequencer to instruct the CPU to process a macroblock"; 477 simcop_dma_irq1 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 478 ldc2bridge_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "The LDC2 bridge has generated an error."; 479 icnt_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "An error has been received on the SIMCOP master port."; 480 vlcdj_decode_err_irq 1 rw1c type(cpu_proc_start_irq_status3) "A decode error has been signaled by the VLCDJ module"; 481 done_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when the hardware sequencer finishes the sequence: The sequence step counter has reached the limit. All accelerator and DMA events for the last sequence step have been received."; 482 step3_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 3 is activated by the hardware sequencer"; 483 step2_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 2 is activated by the hardware sequencer"; 484 step1_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 1 is activated by the hardware sequencer"; 485 step0_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when Step 0 is activated by the hardware sequencer"; 486 ldc_block_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a macroblock has been processed"; 487 _ 1 mbz; 488 rot_a 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the ROT a engine"; 489 imx_b_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 490 imx_a_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when iMX has executed a SLEEP instruction."; 491 nsf_irq_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the NSF2 imaging accelerator when processing of a block is done."; 492 vlcdj_bloc_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by VLCDJ when a macroblock has been processed (encode/decode)"; 493 dct_irq 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered when a block has been processed by the DCT module and the filter outcome has been stored to an image buffer."; 494 ldc_frame_irq 1 rw1c type(cpu_proc_start_irq_status3) "This event is triggered by LDC when a full frame has been processed"; 495 simcop_dma_irq0 1 rw1c type(cpu_proc_start_irq_status3) "Event triggered by the SIMCOP DMA. Check SIMCOP DMA IRQ registers."; 496 }; 497 498 constants ldc_r_burst_break_status width(1) "" { 499 LDC_R_BURST_BREAK_0 = 0 "Yes."; 500 LDC_R_BURST_BREAK_1 = 1 "No. OCP transactions must be split"; 501 }; 502 503 constants ldc_r_max_burst_lenght_status width(2) "" { 504 LDC_R_MAX_BURST_LENGHT_0 = 0 "8 x 128"; 505 LDC_R_MAX_BURST_LENGHT_1 = 1 "6 x 128"; 506 LDC_R_MAX_BURST_LENGHT_2 = 2 "4 x 128"; 507 LDC_R_MAX_BURST_LENGHT_3 = 3 "2 x 128"; 508 }; 509 510 constants imx_b_cmd_status width(1) "" { 511 IMX_B_CMD_0 = 0 "Coprocessor bus"; 512 IMX_B_CMD_1 = 1 "iMX B instruction read / write"; 513 }; 514 515 constants imx_a_cmd_status width(2) "" { 516 IMX_A_CMD_0 = 0 "Coprocessor bus"; 517 IMX_A_CMD_1 = 1 "iMX A instruction read/write"; 518 IMX_A_CMD_2 = 2 "iMX B instruction read/write"; 519 }; 520 521 constants huff_status width(1) "" { 522 HUFF_0 = 0 "Coprocessor"; 523 HUFF_1 = 1 "VLCDJ Huffman table read"; 524 }; 525 526 constants quant_status width(1) "" { 527 QUANT_0 = 0 "Coprocessor bus"; 528 QUANT_1 = 1 "VLCDJ quantization table read"; 529 }; 530 531 constants ldc_lut_status width(1) "" { 532 LDC_LUT_0 = 0 "Coprocessor bus"; 533 LDC_LUT_1 = 1 "The LDC module could access the LDC LUT."; 534 }; 535 536 constants ldc_input_status width(2) "" { 537 LDC_INPUT_0 = 0 "No input memory attached"; 538 LDC_INPUT_1 = 1 "Use image buffers a and b"; 539 LDC_INPUT_2 = 2 "Use image buffers a, b, c, and d"; 540 LDC_INPUT_3 = 3 "Use LDC private input memory."; 541 }; 542 543 constants nsf_wmem_status width(2) "" { 544 NSF_WMEM_0 = 0 "No working memory attached to NSF2. NSF2 cannot be used."; 545 NSF_WMEM_1 = 1 "iMX A coefficient memory used."; 546 NSF_WMEM_2 = 2 "Image buffers a and b used. Those image buffers cannot be used for other purposes. This setting has higher priority than the context configuration."; 547 NSF_WMEM_3 = 3 "Image buffers a, b, c, and d used. Those image buffers cannot be used for other purposes. This setting has higher priority than the context configuration."; 548 }; 549 550 constants irq3_mode_status width(1) "" { 551 IRQ3_MODE_0 = 0 "The interrupt line is asserted when one of the events enabled in SIMCOP_IRQENABLE_3 is pending."; 552 IRQ3_MODE_1 = 1 "The interrupt line is asserted when all events enabled in SIMCOP_IRQENABLE_3 are pending."; 553 }; 554 555 constants irq2_mode_status width(1) "" { 556 IRQ2_MODE_0 = 0 "The interrupt line is asserted when one of the events enabled in SIMCOP_IRQENABLE_2 is pending."; 557 IRQ2_MODE_1 = 1 "The interrupt line is asserted when all events enabled in SIMCOP_IRQENABLE_2 are pending."; 558 }; 559 560 constants irq1_mode_status width(1) "" { 561 IRQ1_MODE_0 = 0 "The interrupt line is asserted when one of the events enabled in SIMCOP_IRQENABLE_1 is pending."; 562 IRQ1_MODE_1 = 1 "The interrupt line is asserted when all events enabled in SIMCOP_IRQENABLE_1 are pending."; 563 }; 564 565 constants irq0_mode_status width(1) "" { 566 IRQ0_MODE_0 = 0 "The interrupt line is asserted when one of the events enabled in SIMCOP_IRQENABLE_0 is pending."; 567 IRQ0_MODE_1 = 1 "The interrupt line is asserted when all events enabled in SIMCOP_IRQENABLE_0 are pending."; 568 }; 569 570 register simcop_ctrl addr(base, 0x60) "SIMCOP control register" { 571 _ 3 mbz; 572 ldc_r_burst_break 1 rw type(ldc_r_burst_break_status) "Controls if bursts issued by the LDC2 bridge could cross burst length boundaries. When this register is set, the LDC2 bridge only issues aligned bursts. Register can only be used when LDC_R_MAX_BURST_LENGHT is 32, 64, or 128 bytes."; 573 ldc_r_max_burst_lenght 2 rw type(ldc_r_max_burst_lenght_status) "Limits the maximum burst length that could be used by the LDC2 bridge"; 574 _ 1 mbz; 575 ldc_r_tag_cnt 4 rw "Limits the maximum number of outstanding requests to LDC_R_TAG_CNT+1"; 576 _ 1 mbz; 577 ldc_r_tag_ofst 4 rw "First OCP tag ID that can be used by LDC reads.Software must prevent overlap with tags generated by the SIMCOP DMA.Typically this value should be equal to SIMCP_DMA_CTRL.TAG_CNT+1."; 578 _ 1 mbz; 579 imx_b_cmd 1 rw type(imx_b_cmd_status) "Switch for iMX # command memory"; 580 imx_a_cmd 2 rw type(imx_a_cmd_status) "Switch for iMX A command memory"; 581 huff 1 rw type(huff_status) "Switch for Huffman table"; 582 quant 1 rw type(quant_status) "Switch for quantization table"; 583 _ 1 mbz; 584 ldc_lut 1 rw type(ldc_lut_status) "Switch for LDC LUT"; 585 ldc_input 2 rw type(ldc_input_status) "Selects input data buffer for LDC. Memories attached to LDC as working memories cannot be used by any other accelerators. HWSEQ or HWSEQ software override settings are ignored for those memories."; 586 nsf_wmem 2 rw type(nsf_wmem_status) "Selects working memory for NSF. Memories attached to NSF as working memories cannot be used by any other accelerators. HWSEQ or HWSEQ software override settings are ignored for those memories."; 587 irq3_mode 1 rw type(irq3_mode_status) "Interrupt generation method"; 588 irq2_mode 1 rw type(irq2_mode_status) "Interrupt generation method"; 589 irq1_mode 1 rw type(irq1_mode_status) "Interrupt generation method"; 590 irq0_mode 1 rw type(irq0_mode_status) "Interrupt generation method"; 591 }; 592 593 constants rot_a_status width(1) "" { 594 ROT_A_0_w_16 = 0 "Request shutdown of the submodule. No effect if the submodule clock is already off."; 595 ROT_A_0_r_16 = 0 "The submodule is off"; 596 ROT_A_1_r_16 = 1 "The submodule is on"; 597 ROT_A_1_w_16 = 1 "Request enable of the submodule. No effect if the submodule clock is already off."; 598 }; 599 600 constants imx_b_status width(1) "" { 601 IMX_B_0_w = 0 "Request shutdown of the submodule. No effect if the submodule clock is already off."; 602 IMX_B_0_r = 0 "The submodule is off."; 603 IMX_B_1_r = 1 "The submodule is on."; 604 IMX_B_1_w = 1 "Request enable of the submodule. No effect if the submodule clock is already off."; 605 }; 606 607 register simcop_clkctrl addr(base, 0x64) "SIMCOP clock control register. Use to enable/disable the interface and functional clock of SIMCOP submodules. Disabled modules cannot be accessed" { 608 _ 24 mbz; 609 rot_a 1 rw type(rot_a_status) "ROT A"; 610 imx_b 1 rw type(imx_b_status) "iMX B"; 611 imx_a 1 rw type(imx_b_status) "iMX A"; 612 nsf2 1 rw type(imx_b_status) "NSF2"; 613 vlcdj 1 rw type(imx_b_status) "VLCDJ"; 614 dct 1 rw type(imx_b_status) "DCT"; 615 ldc 1 rw type(imx_b_status) "LDC"; 616 dma 1 rw type(imx_b_status) "DMA"; 617 }; 618};