1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_sgx_cm2.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_sgx_cm2 msbfirst ( addr base ) "" {
29    
30
31    constants clkactivity_sgx_fclk_status width(1) "" {
32        CLKACTIVITY_SGX_FCLK_0_r = 0 "Corresponding clock is definitely gated";
33        CLKACTIVITY_SGX_FCLK_1_r = 1 "Corresponding clock is running or gating/ungating transition is ongoing";
34    };
35
36    constants clktrctrl_status width(2) "" {
37        CLKTRCTRL_0 = 0 "NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur.";
38        CLKTRCTRL_1 = 1 "SW_SLEEP: Start a software forced sleep transition on the domain.";
39        CLKTRCTRL_2 = 2 "SW_WKUP: Start a software forced wake-up transition on the domain.";
40        CLKTRCTRL_3 = 3 "HW_AUTO: Automatic transition is enabled. Sleep and wakeup transition are based upon hardware conditions.";
41    };
42    
43    register cm_sgx_clkstctrl addr(base, 0x0) "This register enables the SGX domain power state transition. It controls the hardware supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." {
44        _ 22 mbz;
45        clkactivity_sgx_fclk 1 ro type(clkactivity_sgx_fclk_status) "This field indicates the state of the SGX_FCLK clock in the domain. [warm reset insensitive]";
46        clkactivity_sgx_l3_iclk 1 ro type(clkactivity_sgx_fclk_status) "This field indicates the state of the SGX_L3_ICLK clock in the domain. [warm reset insensitive]";
47        _ 6 mbz;
48        clktrctrl 2 rw type(clktrctrl_status) "Controls the clock state transition of the SGX clock domain.";
49    };
50
51    constants l3_2_statdep_status width(1) "" {
52        L3_2_STATDEP_1_r = 1 "Dependency is enabled";
53    };
54
55    constants l3_1_statdep_status width(1) "" {
56        L3_1_STATDEP_0 = 0 "Dependency is disabled";
57        L3_1_STATDEP_1 = 1 "Dependency is enabled";
58    };
59    
60    register cm_sgx_staticdep addr(base, 0x4) "This register controls the static domain depedencies from SGX domain towards 'target' domains. It is relevant only for domain having system initiator(s)." {
61        _ 25 mbz;
62        l3_2_statdep 1 ro type(l3_2_statdep_status) "Static dependency towards L3_2 clock domain";
63        l3_1_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards L3_1 clock domain";
64        memif_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards MEMIF clock domain";
65        _ 1 mbz;
66        ivahd_statdep 1 rw type(l3_1_statdep_status) "Static dependency towards IVAHD clock domain";
67        _ 2 mbz;
68    };
69    
70    register cm_sgx_dynamicdep addr(base, 0x8) "This register controls the dynamic domain depedencies from SGX domain towards 'target' domains. It is relevant only for domain having INTRCONN master port(s)." {
71        _ 25 mbz;
72        l3_2_dyndep 1 ro type(l3_1_statdep_status) "Dynamic dependency towards L3_2 clock domain";
73        _ 6 mbz;
74    };
75
76    constants clksel_sgx_fclk_status width(1) "" {
77        CLKSEL_SGX_FCLK_0 = 0 "Functional clock is sourced from DPLL_CORE HSDIVIDER";
78        CLKSEL_SGX_FCLK_1 = 1 "Functional clock is sourced from DPLL_PER HSDIVIDER";
79    };
80
81    constants stbyst_status width(1) "" {
82        STBYST_0_r = 0 "Module is functional (not in standby)";
83        STBYST_1_r = 1 "Module is in standby";
84    };
85
86    constants idlest_status width(2) "" {
87        IDLEST_0_r = 0 "Module is fully functional, including INTRCONN";
88        IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
89        IDLEST_2_r = 2 "Module is in idle mode (only INTRCONN part). It is functional if using separate functional clock";
90        IDLEST_3_r = 3 "Module is disabled and cannot be accessed";
91    };
92
93    constants modulemode_status width(2) "" {
94        MODULEMODE_0 = 0 "Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup).";
95        MODULEMODE_1_r = 1 "Reserved";
96        MODULEMODE_2 = 2 "Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen.";
97        MODULEMODE_3_r = 3 "Reserved";
98    };
99    
100    register cm_sgx_sgx_clkctrl addr(base, 0x20) "This register manages the SGX clocks." {
101        _ 7 mbz;
102        clksel_sgx_fclk 1 rw type(clksel_sgx_fclk_status) "Select the source of SGX_FCLK";
103        _ 5 mbz;
104        stbyst 1 ro type(stbyst_status) "Module standby status. [warm reset insensitive]";
105        idlest 2 ro type(idlest_status) "Module idle status. [warm reset insensitive]";
106        _ 14 mbz;
107        modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
108    };
109};