1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_scrm.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_scrm msbfirst ( addr base ) "" {
29    
30    
31    register revision_scrm addr(base, 0x0) "This register contains the IP revision code for the SCRM." {
32        _ 24 mbz;
33        rev 8 ro "Revision Number";
34    };
35    
36    register clksetuptime addr(base, 0x100) "This register holds the clock setup time counters of the system clock source supplier." {
37        _ 10 mbz;
38        downtime 6 rw "Holds the number of 32 kHz clock cycles it takes to gate the clock source supplier.";
39        _ 4 mbz;
40        setuptime 12 rw "Holds the number of 32 kHz clock cycles it takes to stabilize the clock source supplier.";
41    };
42    
43    register pmicsetuptime addr(base, 0x104) "This register holds the setup time counters for the sleep mode of the clock-source generator power supply (the power supply in external connected PMIC or LDO)." {
44        _ 10 mbz;
45        wakeuptime 6 rw "Holds the number of 32 kHz clock cycles it takes to exit the clock-source generator power supply from sleep mode. SCRM starts Wakeup-time counter by activation of power request.";
46        _ 10 mbz;
47        sleeptime 6 rw "Holds the number of 32 kHz clock cycles it takes to enter the clock source generator power supply in sleep mode. SCRM activates Sleep-time counter by deactivation of power request.";
48    };
49
50    constants enable_ext_status width(1) "" {
51        ENABLE_EXT_0 = 0 "The alternate system clock version is disabled.";
52        ENABLE_EXT_1 = 1 "The alternate system clock version is enabled.";
53    };
54
55    constants mode_status width(2) "" {
56        MODE_0 = 0 "The alternate system clock source supplier is powered-down.";
57        MODE_1 = 1 "The alternate system clock source supplier is active.";
58        MODE_2 = 2 "The alternate system clock source supplier is bypassed.";
59        MODE_3 = 3 "Reserved";
60    };
61    
62    register altclksrc addr(base, 0x110) "This register controls the alternate system clock source supplier." {
63        _ 28 mbz;
64        enable_ext 1 rw type(enable_ext_status) "This bit allows to enable and disable the output alternate system clock version. This bit is intended to be used in order to gate this clock path while the source is stabilizing.";
65        enable_int 1 rw type(enable_ext_status) "This bit allows to enable and disable the alternate system clock version used to generate the auxiliary clocks. This bit is intended to be used in order to gate this clock path while the source is stabilizing and also to gate this clock path while switching the auxiliary clock paths on / from this possible source.";
66        mode 2 rw type(mode_status) "This bit field defines the functional mode of the alternate system clock supplier.";
67    };
68
69    constants sysclk_status width(1) "" {
70        SYSCLK_0 = 0 "The system clock version for the external C2C interface is disabled.";
71        SYSCLK_1 = 1 "The system clock version for the external C2C interface is enabled.";
72    };
73    
74    register c2cclkm addr(base, 0x11C) "This register controls the clocks of the external C2C interface." {
75        _ 30 mbz;
76        sysclk 1 rw type(sysclk_status) "This bit allows to enable and disable the system clock version of the external C2C interface.";
77        clk_32khz 1 rw type(sysclk_status) "This bit allows to enable and disable the 32 kHz clock version of the external C2C interface.";
78    };
79    
80    register extclkreq addr(base, 0x200) "This register holds qualifiers for the external clock request." {
81        _ 31 mbz;
82        polarity 1 rw type(mode_status) "This bit defines the active level of the external clock request.";
83    };
84    
85    register accclkreq addr(base, 0x204) "This register holds qualifiers for the accurate clock request." {
86        _ 31 mbz;
87        polarity 1 rw type(mode_status) "This bit defines the active level of the accurate clock request.";
88    };
89    
90    register pwrreq addr(base, 0x208) "This register holds qualifiers for the external power request." {
91        _ 31 mbz;
92        polarity 1 rw type(mode_status) "This bit defines the active level of the external power request.";
93    };
94
95    constants mapping_status width(3) "" {
96        MAPPING_0 = 0 "The auxiliary clock request #0 is mapped on the auxiliary clock #0.";
97        MAPPING_1 = 1 "The auxiliary clock request #0 is mapped on the auxiliary clock #1.";
98        MAPPING_2 = 2 "The auxiliary clock request #0 is mapped on the auxiliary clock #2.";
99        MAPPING_3 = 3 "The auxiliary clock request #0 is mapped on the auxiliary clock #3.";
100        MAPPING_4 = 4 "The auxiliary clock request #0 is mapped on the auxiliary clock #4.";
101        MAPPING_5 = 5 "The auxiliary clock request #0 is mapped on the auxiliary clock #5.";
102        MAPPING_6 = 6 "Reserved";
103        MAPPING_7 = 7 "Reserved";
104    };
105    
106    register auxclkreq0 addr(base, 0x210) "This register holds qualifiers for the auxiliary clock request #0." {
107        _ 27 mbz;
108        mapping 3 rw type(mapping_status) "This field allows re-mapping the auxiliary clock request #0 on another auxiliary clock output than auxiliary clock #0.";
109        accuracy 1 rw type(mode_status) "This bit qualifies the auxiliary clock request #0 as an accurate clock request.";
110        polarity 1 rw type(mode_status) "This bit defines the active level of the auxiliary clock request #0.";
111    };
112    
113    register auxclkreq1 addr(base, 0x214) "This register holds qualifiers for the auxiliary clock request #1." {
114        _ 27 mbz;
115        mapping 3 rw type(mapping_status) "This field allows re-mapping the auxiliary clock request #1 on another auxiliary clock output than auxiliary clock #1.";
116        accuracy 1 rw type(mode_status) "This bit qualifies the auxiliary clock request #1 as an accurate clock request.";
117        polarity 1 rw type(mode_status) "This bit defines the active level of the auxiliary clock request #1.";
118    };
119    
120    register auxclkreq2 addr(base, 0x218) "This register holds qualifiers for the auxiliary clock request #2." {
121        _ 27 mbz;
122        mapping 3 rw type(mapping_status) "This field allows re-mapping the auxiliary clock request #2 on another auxiliary clock output than auxiliary clock #2.";
123        accuracy 1 rw type(mode_status) "This bit qualifies the auxiliary clock request #2 as an accurate clock request.";
124        polarity 1 rw type(mode_status) "This bit defines the active level of the auxiliary clock request #2.";
125    };
126    
127    register auxclkreq3 addr(base, 0x21C) "This register holds qualifiers for the auxiliary clock request #3." {
128        _ 27 mbz;
129        mapping 3 rw type(mapping_status) "This field allows re-mapping the auxiliary clock request #3 on another auxiliary clock output than auxiliary clock #3.";
130        accuracy 1 rw type(mode_status) "This bit qualifies the auxiliary clock request #3 as an accurate clock request.";
131        polarity 1 rw type(mode_status) "This bit defines the active level of the auxiliary clock request #3.";
132    };
133    
134    register auxclkreq4 addr(base, 0x220) "This register holds qualifiers for the auxiliary clock request #4." {
135        _ 27 mbz;
136        mapping 3 rw type(mapping_status) "This field allows re-mapping the auxiliary clock request #4 on another auxiliary clock output than auxiliary clock #4.";
137        accuracy 1 rw type(mode_status) "This bit qualifies the auxiliary clock request #4 as an accurate clock request.";
138        polarity 1 rw type(mode_status) "This bit defines the active level of the auxiliary clock request #4.";
139    };
140    
141    register auxclkreq5 addr(base, 0x224) "This register holds qualifiers for the auxiliary clock request #5." {
142        _ 27 mbz;
143        mapping 3 rw type(mapping_status) "This field allows re-mapping the auxiliary clock request #5 on another auxiliary clock output than auxiliary clock #5.";
144        accuracy 1 rw type(mode_status) "This bit qualifies the auxiliary clock request #5 as an accurate clock request.";
145        polarity 1 rw type(mode_status) "This bit defines the active level of the auxiliary clock request #5.";
146    };
147    
148    register c2cclkreq addr(base, 0x234) "This register holds qualifiers for the external C2C interface clock request." {
149        _ 30 mbz;
150        accuracy 1 rw type(sysclk_status) "This bit qualifies the external C2C interface clock request as an accurate clock request.";
151        polarity 1 rw type(sysclk_status) "This bit defines the active level of the external C2C interface clock request.";
152    };
153
154    constants clkdiv_status width(4) "" {
155        CLKDIV_0 = 0 "The auxiliary clock #0 is divided by 1.";
156        CLKDIV_1 = 1 "The auxiliary clock #0 is divided by 2.";
157        CLKDIV_2 = 2 "The auxiliary clock #0 is divided by 3.";
158        CLKDIV_3 = 3 "The auxiliary clock #0 is divided by 4.";
159        CLKDIV_4 = 4 "The auxiliary clock #0 is divided by 5.";
160        CLKDIV_5 = 5 "The auxiliary clock #0 is divided by 6.";
161        CLKDIV_6 = 6 "The auxiliary clock #0 is divided by 7.";
162        CLKDIV_7 = 7 "The auxiliary clock #0 is divided by 8.";
163        CLKDIV_8 = 8 "The auxiliary clock #0 is divided by 9.";
164        CLKDIV_9 = 9 "The auxiliary clock #0 is divided by 10.";
165        CLKDIV_10 = 10 "The auxiliary clock #0 is divided by 11.";
166        CLKDIV_11 = 11 "The auxiliary clock #0 is divided by 12.";
167        CLKDIV_12 = 12 "The auxiliary clock #0 is divided by 13.";
168        CLKDIV_13 = 13 "The auxiliary clock #0 is divided by 14.";
169        CLKDIV_14 = 14 "The auxiliary clock #0 is divided by 15.";
170        CLKDIV_15 = 15 "The auxiliary clock #0 is divided by 16.";
171    };
172
173    constants disableclk_status width(1) "" {
174        DISABLECLK_0 = 0 "The auxiliary clock #0 is gated upon normal condition: auxiliary clock requests mapped on this path or ENABLE bit set.";
175        DISABLECLK_1 = 1 "The auxiliary clock #0 is gated wihout conditon.";
176    };
177
178    constants srcselect_status width(2) "" {
179        SRCSELECT_0 = 0 "The clock source is the system clock.";
180        SRCSELECT_1 = 1 "The clock source is the version from the CORE DPLL.";
181        SRCSELECT_2 = 2 "The clock source is the version from the PER DPLL.";
182        SRCSELECT_3 = 3 "The clock source is the alternate clock.";
183    };
184
185    constants polarity_status width(1) "" {
186        POLARITY_0_10 = 0 "The auxiliary clock #0 is gated low.";
187        POLARITY_1_10 = 1 "The auxiliary clock #0 is gated high.";
188    };
189    
190    register auxclk0 addr(base, 0x310) "This register holds qualifiers for the auxiliary clock #0." {
191        _ 12 mbz;
192        clkdiv 4 rw type(clkdiv_status) "This field holds the divider value for the auxiliary clock #0.";
193        _ 6 mbz;
194        disableclk 1 rw type(disableclk_status) "This bit allows to gate the auxiliary clock #0 without condition. This is bit is intended to be used only when the SOC is not clock provider.";
195        enable 1 rw type(mode_status) "This bit allows to request the auxiliary clock #0 by software.";
196        _ 5 mbz;
197        srcselect 2 rw type(srcselect_status) "This field allows selecting the clock source of the auxiliary clock #0.";
198        polarity 1 rw type(polarity_status) "This bit defines the output level when the auxiliary clock #0 is gated.";
199    };
200
201    constants clkdiv_status1 width(4) "" {
202        CLKDIV_0_1 = 0 "The auxiliary clock #1 is divided by 1.";
203        CLKDIV_1_1 = 1 "The auxiliary clock #1 is divided by 2.";
204        CLKDIV_2_1 = 2 "The auxiliary clock #1 is divided by 3.";
205        CLKDIV_3_1 = 3 "The auxiliary clock #1 is divided by 4.";
206        CLKDIV_4_1 = 4 "The auxiliary clock #1 is divided by 5.";
207        CLKDIV_5_1 = 5 "The auxiliary clock #1 is divided by 6.";
208        CLKDIV_6_1 = 6 "The auxiliary clock #1 is divided by 7.";
209        CLKDIV_7_1 = 7 "The auxiliary clock #1 is divided by 8.";
210        CLKDIV_8_1 = 8 "The auxiliary clock #1 is divided by 9.";
211        CLKDIV_9_1 = 9 "The auxiliary clock #1 is divided by 10.";
212        CLKDIV_10_1 = 10 "The auxiliary clock #1 is divided by 11.";
213        CLKDIV_11_1 = 11 "The auxiliary clock #1 is divided by 12.";
214        CLKDIV_12_1 = 12 "The auxiliary clock #1 is divided by 13.";
215        CLKDIV_13_1 = 13 "The auxiliary clock #1 is divided by 14.";
216        CLKDIV_14_1 = 14 "The auxiliary clock #1 is divided by 15.";
217        CLKDIV_15_1 = 15 "The auxiliary clock #1 is divided by 16.";
218    };
219
220    constants polarity_status1 width(1) "" {
221        POLARITY_0_11 = 0 "The auxiliary clock #1 is gated low.";
222        POLARITY_1_11 = 1 "The auxiliary clock #1 is gated high.";
223    };
224    
225    register auxclk1 addr(base, 0x314) "This register holds qualifiers for the auxiliary clock #1." {
226        _ 12 mbz;
227        clkdiv 4 rw type(clkdiv_status1) "This field holds the divider value for the auxiliary clock #1.";
228        _ 7 mbz;
229        enable 1 rw type(mode_status) "This bit allows to request the auxiliary clock #1 by software.";
230        _ 5 mbz;
231        srcselect 2 rw type(srcselect_status) "This field allows selecting the clock source of the auxiliary clock #1.";
232        polarity 1 rw type(polarity_status1) "This bit defines the output level when the auxiliary clock #1 is gated.";
233    };
234
235    constants clkdiv_status2 width(4) "" {
236        CLKDIV_0_2 = 0 "The auxiliary clock #2 is divided by 1.";
237        CLKDIV_1_2 = 1 "The auxiliary clock #2 is divided by 2.";
238        CLKDIV_2_2 = 2 "The auxiliary clock #2 is divided by 3.";
239        CLKDIV_3_2 = 3 "The auxiliary clock #2 is divided by 4.";
240        CLKDIV_4_2 = 4 "The auxiliary clock #2 is divided by 5.";
241        CLKDIV_5_2 = 5 "The auxiliary clock #2 is divided by 6.";
242        CLKDIV_6_2 = 6 "The auxiliary clock #2 is divided by 7.";
243        CLKDIV_7_2 = 7 "The auxiliary clock #2 is divided by 8.";
244        CLKDIV_8_2 = 8 "The auxiliary clock #2 is divided by 9.";
245        CLKDIV_9_2 = 9 "The auxiliary clock #2 is divided by 10.";
246        CLKDIV_10_2 = 10 "The auxiliary clock #2 is divided by 11.";
247        CLKDIV_11_2 = 11 "The auxiliary clock #2 is divided by 12.";
248        CLKDIV_12_2 = 12 "The auxiliary clock #2 is divided by 13.";
249        CLKDIV_13_2 = 13 "The auxiliary clock #2 is divided by 14.";
250        CLKDIV_14_2 = 14 "The auxiliary clock #2 is divided by 15.";
251        CLKDIV_15_2 = 15 "The auxiliary clock #2 is divided by 16.";
252    };
253
254    constants polarity_status2 width(1) "" {
255        POLARITY_0_12 = 0 "The auxiliary clock #2 is gated low.";
256        POLARITY_1_12 = 1 "The auxiliary clock #2 is gated high.";
257    };
258    
259    register auxclk2 addr(base, 0x318) "This register holds qualifiers for the auxiliary clock #2." {
260        _ 12 mbz;
261        clkdiv 4 rw type(clkdiv_status2) "This field holds the divider value for the auxiliary clock #2.";
262        _ 7 mbz;
263        enable 1 rw type(mode_status) "This bit allows to request the auxiliary clock #2 by software.";
264        _ 5 mbz;
265        srcselect 2 rw type(srcselect_status) "This field allows selecting the clock source of the auxiliary clock #2.";
266        polarity 1 rw type(polarity_status2) "This bit defines the output level when the auxiliary clock #2 is gated.";
267    };
268
269    constants clkdiv_status3 width(4) "" {
270        CLKDIV_0_3 = 0 "The auxiliary clock #3 is divided by 1.";
271        CLKDIV_1_3 = 1 "The auxiliary clock #3 is divided by 2.";
272        CLKDIV_2_3 = 2 "The auxiliary clock #3 is divided by 3.";
273        CLKDIV_3_3 = 3 "The auxiliary clock #3 is divided by 4.";
274        CLKDIV_4_3 = 4 "The auxiliary clock #3 is divided by 5.";
275        CLKDIV_5_3 = 5 "The auxiliary clock #3 is divided by 6.";
276        CLKDIV_6_3 = 6 "The auxiliary clock #3 is divided by 7.";
277        CLKDIV_7_3 = 7 "The auxiliary clock #3 is divided by 8.";
278        CLKDIV_8_3 = 8 "The auxiliary clock #3 is divided by 9.";
279        CLKDIV_9_3 = 9 "The auxiliary clock #3 is divided by 10.";
280        CLKDIV_10_3 = 10 "The auxiliary clock #3 is divided by 11.";
281        CLKDIV_11_3 = 11 "The auxiliary clock #3 is divided by 12.";
282        CLKDIV_12_3 = 12 "The auxiliary clock #3 is divided by 13.";
283        CLKDIV_13_3 = 13 "The auxiliary clock #3 is divided by 14.";
284        CLKDIV_14_3 = 14 "The auxiliary clock #3 is divided by 15.";
285        CLKDIV_15_3 = 15 "The auxiliary clock #3 is divided by 16.";
286    };
287
288    constants polarity_status3 width(1) "" {
289        POLARITY_0_13 = 0 "The auxiliary clock #3 is gated low.";
290        POLARITY_1_13 = 1 "The auxiliary clock #3 is gated high.";
291    };
292    
293    register auxclk3 addr(base, 0x31C) "This register holds qualifiers for the auxiliary clock #3." {
294        _ 12 mbz;
295        clkdiv 4 rw type(clkdiv_status3) "This field holds the divider value for the auxiliary clock #3.";
296        _ 7 mbz;
297        enable 1 rw type(mode_status) "This bit allows to request the auxiliary clock #3 by software.";
298        _ 5 mbz;
299        srcselect 2 rw type(srcselect_status) "This field allows selecting the clock source of the auxiliary clock #3.";
300        polarity 1 rw type(polarity_status3) "This bit defines the output level when the auxiliary clock #3 is gated.";
301    };
302
303    constants clkdiv_status4 width(4) "" {
304        CLKDIV_0_4 = 0 "The auxiliary clock #4 is divided by 1.";
305        CLKDIV_1_4 = 1 "The auxiliary clock #4 is divided by 2.";
306        CLKDIV_2_4 = 2 "The auxiliary clock #4 is divided by 3.";
307        CLKDIV_3_4 = 3 "The auxiliary clock #4 is divided by 4.";
308        CLKDIV_4_4 = 4 "The auxiliary clock #4 is divided by 5.";
309        CLKDIV_5_4 = 5 "The auxiliary clock #4 is divided by 6.";
310        CLKDIV_6_4 = 6 "The auxiliary clock #4 is divided by 7.";
311        CLKDIV_7_4 = 7 "The auxiliary clock #4 is divided by 8.";
312        CLKDIV_8_4 = 8 "The auxiliary clock #4 is divided by 9.";
313        CLKDIV_9_4 = 9 "The auxiliary clock #4 is divided by 10.";
314        CLKDIV_10_4 = 10 "The auxiliary clock #4 is divided by 11.";
315        CLKDIV_11_4 = 11 "The auxiliary clock #4 is divided by 12.";
316        CLKDIV_12_4 = 12 "The auxiliary clock #4 is divided by 13.";
317        CLKDIV_13_4 = 13 "The auxiliary clock #4 is divided by 14.";
318        CLKDIV_14_4 = 14 "The auxiliary clock #4 is divided by 15.";
319        CLKDIV_15_4 = 15 "The auxiliary clock #4 is divided by 16.";
320    };
321
322    constants polarity_status4 width(1) "" {
323        POLARITY_0_14 = 0 "The auxiliary clock #4 is gated low.";
324        POLARITY_1_14 = 1 "The auxiliary clock #4 is gated high.";
325    };
326    
327    register auxclk4 addr(base, 0x320) "This register holds qualifiers for the auxiliary clock #4." {
328        _ 12 mbz;
329        clkdiv 4 rw type(clkdiv_status4) "This field holds the divider value for the auxiliary clock #4.";
330        _ 7 mbz;
331        enable 1 rw type(mode_status) "This bit allows to request the auxiliary clock #4 by software.";
332        _ 5 mbz;
333        srcselect 2 rw type(srcselect_status) "This field allows selecting the clock source of the auxiliary clock #4.";
334        polarity 1 rw type(polarity_status4) "This bit defines the output level when the auxiliary clock #4 is gated.";
335    };
336
337    constants clkdiv_status5 width(4) "" {
338        CLKDIV_0_5 = 0 "The auxiliary clock #5 is divided by 1.";
339        CLKDIV_1_5 = 1 "The auxiliary clock #5 is divided by 2.";
340        CLKDIV_2_5 = 2 "The auxiliary clock #5 is divided by 3.";
341        CLKDIV_3_5 = 3 "The auxiliary clock #5 is divided by 4.";
342        CLKDIV_4_5 = 4 "The auxiliary clock #5 is divided by 5.";
343        CLKDIV_5_5 = 5 "The auxiliary clock #5 is divided by 6.";
344        CLKDIV_6_5 = 6 "The auxiliary clock #5 is divided by 7.";
345        CLKDIV_7_5 = 7 "The auxiliary clock #5 is divided by 8.";
346        CLKDIV_8_5 = 8 "The auxiliary clock #5 is divided by 9.";
347        CLKDIV_9_5 = 9 "The auxiliary clock #5 is divided by 10.";
348        CLKDIV_10_5 = 10 "The auxiliary clock #5 is divided by 11.";
349        CLKDIV_11_5 = 11 "The auxiliary clock #5 is divided by 12.";
350        CLKDIV_12_5 = 12 "The auxiliary clock #5 is divided by 13.";
351        CLKDIV_13_5 = 13 "The auxiliary clock #5 is divided by 14.";
352        CLKDIV_14_5 = 14 "The auxiliary clock #5 is divided by 15.";
353        CLKDIV_15_5 = 15 "The auxiliary clock #5 is divided by 16.";
354    };
355
356    constants polarity_status5 width(1) "" {
357        POLARITY_0_15 = 0 "The auxiliary clock #5 is gated low.";
358        POLARITY_1_15 = 1 "The auxiliary clock #5 is gated high.";
359    };
360    
361    register auxclk5 addr(base, 0x324) "This register holds qualifiers for the auxiliary clock #5." {
362        _ 12 mbz;
363        clkdiv 4 rw type(clkdiv_status5) "This field holds the divider value for the auxiliary clock #5.";
364        _ 7 mbz;
365        enable 1 rw type(mode_status) "This bit allows to request the auxiliary clock #5 by software.";
366        _ 5 mbz;
367        srcselect 2 rw type(srcselect_status) "This field allows selecting the clock source of the auxiliary clock #5.";
368        polarity 1 rw type(polarity_status5) "This bit defines the output level when the auxiliary clock #5 is gated.";
369    };
370    
371    register rsttime_reg addr(base, 0x400) "This register holds the reset time counter which is used to extend the reset lines beyond the release of the pad reset." {
372        _ 28 mbz;
373        rsttime 4 rw "Holds the number of 32 kHz clock cycles for which the reset duration is extended. Values 0,1 and 2 are not allowed. 0x0: Reserved. 0x1: Reserved. 0x2: Reserved.";
374    };
375    
376    register c2crstctrl addr(base, 0x41C) "This register controls the release of the external C2C interface reset lines." {
377        _ 30 mbz;
378        warmrst 1 rw type(sysclk_status) "This bit allows to release the warm reset line of the external C2C interface. [warm reset sensitive]";
379        coldrst 1 rw type(sysclk_status) "This bit allows to release the cold reset line of the external C2C interface.";
380    };
381
382    constants pwronrst_status width(1) "" {
383        PWRONRST_0 = 0 "De-asserts the external power-on reset.";
384        PWRONRST_1 = 1 "Asserts the external power-on reset.";
385    };
386    
387    register extpwronrstctrl addr(base, 0x420) "This register allows the software to perform an external power-on reset." {
388        _ 30 mbz;
389        pwronrst 1 rw type(pwronrst_status) "This bit controls the assertion and the de-assertion of the external power-on reset.";
390        enable 1 rw type(mode_status) "This bit must be set to 1 to allow the software to assert the external power-on reset.";
391    };
392
393    constants extwarmrstst_status width(1) "" {
394        EXTWARMRSTST_0 = 0 "No external warm reset occurred.";
395        EXTWARMRSTST_1 = 1 "An external warm reset occurred.";
396    };
397    
398    register extwarmrstst_reg addr(base, 0x510) "This register logs the source of warm reset output. Each bit is set upon release of the warm reset output and must be cleared by software." {
399        _ 31 mbz;
400        extwarmrstst 1 rw1c type(extwarmrstst_status) "This bit logs the external warm reset source.";
401    };
402
403    constants apewarmrstst_status width(1) "" {
404        APEWARMRSTST_0 = 0 "No APE warm reset occurred.";
405        APEWARMRSTST_1 = 1 "An APE warm reset occurred.";
406    };
407    
408    register apewarmrstst_reg addr(base, 0x514) "This register logs the source of warm reset on the APE. Each bit is set upon release of the APE warm reset and must be cleared by software." {
409        _ 30 mbz;
410        apewarmrstst 1 rw1c type(apewarmrstst_status) "This bit logs the APE warm reset source.";
411        _ 1 mbz;
412    };
413
414    constants c2cwarmrstst_status width(1) "" {
415        C2CWARMRSTST_0 = 0 "No C2C warm reset occurred.";
416        C2CWARMRSTST_1 = 1 "A C2C warm reset occurred.";
417    };
418    
419    register c2cwarmrstst_reg addr(base, 0x51C) "This register logs the source of warm reset on the external C2C interface. Each bit is set upon release of the external C2C interface warm reset and must be cleared by software." {
420        _ 28 mbz;
421        c2cwarmrstst 1 rw1c type(c2cwarmrstst_status) "This bit logs the C2C warm reset source.";
422        _ 3 mbz;
423    };
424};