1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_mcbsp1_dsp.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_mcbsp1_dsp msbfirst ( addr base ) "" { 29 30 31 register mcbsplp_drr_reg ro addr(base, 0x0) "McBSPLP data receive register" type(uint32); 32 33 register mcbsplp_dxr_reg wo addr(base, 0x8) "McBSPLP data transmit register" type(uint32); 34 35 constants free_status width(1) "" { 36 FREE_0 = 0 "Free running mode is disabled"; 37 FREE_1 = 1 "Free running mode is enabled"; 38 }; 39 40 constants soft_status width(1) "" { 41 SOFT_0 = 0 "SOFT mode is disabled: the module stops its activity immediately following MSuspend assertion"; 42 SOFT_1 = 1 "SOFT mode is enabled: the module freezes its state after completion of the current operation when MSuspend is asserted"; 43 }; 44 45 constants frst_status width(1) "" { 46 FRST_0 = 0 "Frame-sync logic is reset. Frame-sync signal FSG is not generated by the sample-rate generator"; 47 FRST_1 = 1 "Frame-sync signal FSG is generated after (FPER+1) number of CLKG clocks; that is, all frame counters are loaded with their programmed values"; 48 }; 49 50 constants grst_status width(1) "" { 51 GRST_0 = 0 "SRG is reset"; 52 GRST_1 = 1 "SRG is pulled out of reset. CLKG is driven as per programmed value in SRG registers (SRGR[1,2])"; 53 }; 54 55 constants xintm_status width(2) "" { 56 XINTM_0 = 0 "XINT is driven by XRDY"; 57 XINTM_1 = 1 "XINT generated by end-of-frame"; 58 XINTM_2 = 2 "XINT generated by a new frame synchronization"; 59 XINTM_3 = 3 "XINT generated by XSYNCERR"; 60 }; 61 62 constants xsyncerr_status width(1) "" { 63 XSYNCERR_0 = 0 "No synchronization error"; 64 XSYNCERR_1 = 1 "Synchronization error detected by McBSP"; 65 }; 66 67 constants xempty_status width(1) "" { 68 XEMPTY_0_r = 0 "XSR is empty"; 69 XEMPTY_1_r = 1 "XSR is not empty"; 70 }; 71 72 constants xrdy_status width(1) "" { 73 XRDY_0_r = 0 "Transmitter is not ready."; 74 XRDY_1_r = 1 "Transmitter is ready for new data in DXR"; 75 }; 76 77 constants xrst_status width(1) "" { 78 XRST_0 = 0 "The serial port transmitter is disabled and in reset state."; 79 XRST_1 = 1 "The serial port transmitter is enabled."; 80 }; 81 82 register mcbsplp_spcr2_reg addr(base, 0x10) "McBSPLP serial port control register 2" { 83 _ 22 mbz; 84 free 1 rw type(free_status) "Free Running Mode (When this bit is set, the module ignores the Msuspend input)"; 85 soft 1 rw type(soft_status) "Soft Bit"; 86 frst 1 rw type(frst_status) "Frame-Sync Generator Reset"; 87 grst 1 rw type(grst_status) "Sample-Rate Generator Reset"; 88 xintm 2 rw type(xintm_status) "Transmit Interrupt Mode (legacy)"; 89 xsyncerr 1 rw type(xsyncerr_status) "Transmit Synchronization Error (writing 0 to this bit clear the legacy transmit interrupt if asserted due to XSYNCERR condition)"; 90 xempty 1 ro type(xempty_status) "Transmit Shift Register XSR Empty"; 91 xrdy 1 ro type(xrdy_status) "Transmitter ready"; 92 xrst 1 rw type(xrst_status) "Transmitter reset. This resets and enables the transmitter."; 93 }; 94 95 constants alb_status width(1) "" { 96 ALB_0 = 0 "Analog loopback mode disabled"; 97 ALB_1 = 1 "Analog loopback mode enabled"; 98 }; 99 100 constants rjust_status width(2) "" { 101 RJUST_0 = 0 "Right-justify and zero-fill MSBs in DRR"; 102 RJUST_1 = 1 "Right-justify and sign-extend MSBs in DRR"; 103 RJUST_2 = 2 "Left-justify and zero-fill LSBs in DRR"; 104 RJUST_3 = 3 "Reserved"; 105 }; 106 107 constants dxena_status width(1) "" { 108 DXENA_0 = 0 "DX enabler is off"; 109 DXENA_1 = 1 "DX enabler is on"; 110 }; 111 112 constants rintm_status width(2) "" { 113 RINTM_0 = 0 "RINT driven by RRDY (that is, end of word) and end of frame in A-bis mode"; 114 RINTM_1 = 1 "RINT generated by end-of-block or end-of-frame in multichannel operation"; 115 RINTM_2 = 2 "RINT generated by a new frame synchronization"; 116 RINTM_3 = 3 "RINT generated by RSYNCERR"; 117 }; 118 119 constants rfull_status width(1) "" { 120 RFULL_0_r = 0 "DRR is not read, RB is full and RSR is also full with new word"; 121 RFULL_1_r = 1 "RB is not in overrun condition"; 122 }; 123 124 constants rrdy_status width(1) "" { 125 RRDY_0_r = 0 "Receiver is not ready"; 126 RRDY_1_r = 1 "Receiver is ready with data to be read from DRR"; 127 }; 128 129 constants rrst_status width(1) "" { 130 RRST_0 = 0 "The serial port receiver is disabled and in reset state."; 131 RRST_1 = 1 "The serial port receiver is enabled."; 132 }; 133 134 register mcbsplp_spcr1_reg addr(base, 0x14) "McBSPLP serial port control register 1" { 135 _ 16 mbz; 136 alb 1 rw type(alb_status) "Analog Loopback Mode"; 137 rjust 2 rw type(rjust_status) "Receive Sign-Extension and Justification Mode"; 138 _ 5 mbz; 139 dxena 1 rw type(dxena_status) "DX Enabler"; 140 _ 1 mbz; 141 rintm 2 rw type(rintm_status) "Receive Interrupt Mode (legacy)"; 142 rsyncerr 1 rw type(xsyncerr_status) "Receive Synchronization Error (writing 0 to this bit clear the legacy receive interrupt if asserted due to RSYNCERR condition)"; 143 rfull 1 ro type(rfull_status) "Receive Shift Register (RSR]) Full"; 144 rrdy 1 ro type(rrdy_status) "Receiver Ready"; 145 rrst 1 rw type(rrst_status) "Receiver reset. This resets and enables the receiver."; 146 }; 147 148 constants rphase_status width(1) "" { 149 RPHASE_0 = 0 "Single-phase frame"; 150 RPHASE_1 = 1 "Dual-phase frame"; 151 }; 152 153 constants rwdlen2_status width(3) "" { 154 RWDLEN2_0 = 0 "8 bits"; 155 RWDLEN2_1 = 1 "12 bits"; 156 RWDLEN2_2 = 2 "16 bits"; 157 RWDLEN2_3 = 3 "20 bits"; 158 RWDLEN2_4 = 4 "24 bits"; 159 RWDLEN2_5 = 5 "32 bits"; 160 RWDLEN2_6 = 6 "Reserved (do not use)"; 161 RWDLEN2_7 = 7 "Reserved (do not use)"; 162 }; 163 164 constants rreverse_status width(2) "" { 165 RREVERSE_0 = 0 "Data transfer starts with MSB first."; 166 RREVERSE_1 = 1 "Data transfer starts with LSB first."; 167 RREVERSE_2 = 2 "Reserved (do not use)"; 168 RREVERSE_3 = 3 "Reserved (do not use)"; 169 }; 170 171 constants rdatdly_status width(2) "" { 172 RDATDLY_0 = 0 "0-bit data delay"; 173 RDATDLY_1 = 1 "1-bit data delay"; 174 RDATDLY_2 = 2 "2-bit data delay"; 175 RDATDLY_3 = 3 "Reserved"; 176 }; 177 178 register mcbsplp_rcr2_reg addr(base, 0x18) "McBSPLP receive control register 2" { 179 _ 16 mbz; 180 rphase 1 rw type(rphase_status) "Receive Phases"; 181 rfrlen2 7 rw "Receive Frame Length 2 Single-phase frame selected: RFRLEN2=don't care Dual-phase frame selected: RFRLEN2=000 0000 - 1 word per second phase (other values are reserved)"; 182 rwdlen2 3 rw type(rwdlen2_status) "Receive Word Length 2"; 183 rreverse 2 rw type(rreverse_status) "Receive reverse mode."; 184 _ 1 mbz; 185 rdatdly 2 rw type(rdatdly_status) "Receive Data Delay"; 186 }; 187 188 register mcbsplp_rcr1_reg addr(base, 0x1C) "McBSPLP receive control register 1" { 189 _ 17 mbz; 190 rfrlen1 7 rw "Receive Frame Length 1 Single-phase frame selected: RFRLEN1=000 0000 - 1 word per frame RFRLEN1=000 0001 - 2 words per frame RFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: RFRLEN1=000 0000 - 1 word per phase (other values are reserved)"; 191 rwdlen1 3 rw type(rwdlen2_status) "Receive Word Length 1"; 192 _ 5 mbz; 193 }; 194 195 register mcbsplp_xcr2_reg addr(base, 0x20) "McBSPLP transmit control register 2" { 196 _ 16 mbz; 197 xphase 1 rw type(rphase_status) "Transmit Phases"; 198 xfrlen2 7 rw "Transmit Frame Length 2 Single-phase frame selected: XFRLEN2=don't care Dual-phase frame selected: XFRLEN2=000 0000 - 1 word per second phase (other values are reserved)"; 199 xwdlen2 3 rw type(rwdlen2_status) "Transmit Word Length 2"; 200 xreverse 2 rw type(rreverse_status) "Transmit reverse mode."; 201 _ 1 mbz; 202 xdatdly 2 rw type(rdatdly_status) "Transmit Data Delay"; 203 }; 204 205 register mcbsplp_xcr1_reg addr(base, 0x24) "McBSPLP transmit control register 1" { 206 _ 17 mbz; 207 xfrlen1 7 rw "Transmit Frame Length 1 Single-phase frame selected: XFRLEN1=000 0000 - 1 word per frame XFRLEN1=000 0001 - 2 words per frame XFRLEN1=111 1111 - 128 words per frame Dual-phase frame selected: XFRLEN1=000 0000 - 1 word per phase (other values are reserved)"; 208 xwdlen1 3 rw type(rwdlen2_status) "Transmit Word Length 1"; 209 _ 5 mbz; 210 }; 211 212 constants gsync_status width(1) "" { 213 GSYNC_0 = 0 "The SRG clock (CLKG) is free running."; 214 GSYNC_1 = 1 "The SRG clock (CLKG) is running. But CLKG is resynchronized and frame-sync signal (FSG) is generated only after detecting the receive frame-sync signal (FSR). Also, frame period, FPER, is a don't care because the period is dictated by the external frame-sync pulse."; 215 }; 216 217 constants clksp_status width(1) "" { 218 CLKSP_0 = 0 "Rising edge of CLKG and FSG."; 219 CLKSP_1 = 1 "Falling edge of CLKG and FSG."; 220 }; 221 222 constants clksm_status width(1) "" { 223 CLKSM_0 = 0 "SCLKME=0: SRG clock derived from the CLKS pin. SCLKME=1: SRG clock derived from the CLKRI pin."; 224 CLKSM_1 = 1 "SCLKME=0: SRG clock derived from the CPU clock. SCLKME=1: SRG clock derived from the CLKXI clock."; 225 }; 226 227 constants fsgm_status width(1) "" { 228 FSGM_0 = 0 "Transmit frame-sync signal (FSX) is generated when transmit buffer is not empty When FSGM=0, FPER and FWID are used to determine the frame-sync period and width (external FSX is gated by the buffer empty condition)."; 229 FSGM_1 = 1 "Transmit frame-sync signal driven by the SRG frame-sync signal, FSG."; 230 }; 231 232 register mcbsplp_srgr2_reg addr(base, 0x28) "McBSPLP sample rate generator register 2" { 233 _ 16 mbz; 234 gsync 1 rw type(gsync_status) ""; 235 clksp 1 rw type(clksp_status) "CLKS Polarity Clock Edge Select Only used when the external clock CLKS drives the SRG clock (CLKSM=0)."; 236 clksm 1 rw type(clksm_status) "McBSPLP Sample Rate Generator Clock Mode"; 237 fsgm 1 rw type(fsgm_status) "Sample Rate Generator Transmit Frame-Synchronization Mode Used when FSXM=1 in the PCR."; 238 fper 12 rw "Frame Period. This field plus 1 determines when the next frame-sync signal becomes active. Range: 1 to 4096 CLKG periods"; 239 }; 240 241 register mcbsplp_srgr1_reg addr(base, 0x2C) "McBSPLP sample rate generator register 1" { 242 _ 16 mbz; 243 fwid 8 rw "Frame Width. This field plus 1 determines the width of the frame-sync pulse, FSG, during its active period. Range: 1 to 256 CLKG periods."; 244 clkgdv 8 rw "Sample Rate Generator Clock Divider This value is used as the divide-down number to generate the required SRG clock frequency. Default value is 1."; 245 }; 246 247 constants xmcme_status width(1) "" { 248 XMCME_0 = 0 "2-partition mode: Only partitions A and B are used. You can control up to 32 channels in the transmit multichannel selection mode selected with the XMCM bits. If XMCM = 01b or 10b, assign 16 channels to partition A with the XPABLK bits. Assign 16 channels to partition B with the XPBBLK bits. If XMCM = 11b (for symmetric transmission and reception), assign 16 channels to receive partition A with the RPABLK bits. Assign 16 channels to receive partition B with the RPBBLK bits. You control the channels with the appropriate transmit channel enable registers: XCERA: Channels in partition A XCERB: Channels in partition B"; 249 XMCME_1 = 1 "8-partition mode: All partitions (A through H) are used. You can control up to 128 channels in the transmit multichannel selection mode selected with the XMCM bits. You control the channels with the appropriate transmit channel enable registers: XCERA: Channels 0 through 15 XCERB: Channels 16 through 31 XCERC: Channels 32 through 47 XCERD: Channels 48 through 63 XCERE: Channels 64 through 79 XCERF: Channels 80 through 95 XCERG: Channels 96 through 111 XCERH: Channels 112 through 127"; 250 }; 251 252 constants xpbblk_status width(2) "" { 253 XPBBLK_0 = 0 "Block 1. Channel 16 to channel 31"; 254 XPBBLK_1 = 1 "Block 3. Channel 48 to channel 63"; 255 XPBBLK_2 = 2 "Block 5. Channel 80 to channel 95"; 256 XPBBLK_3 = 3 "Block 7. Channel 112 to channel 127"; 257 }; 258 259 constants xpablk_status width(2) "" { 260 XPABLK_0 = 0 "Block 0. Channel 0 to channel 15"; 261 XPABLK_1 = 1 "Block 2. Channel 32 to channel 47"; 262 XPABLK_2 = 2 "Block 4. Channel 64 to channel 79"; 263 XPABLK_3 = 3 "Block 6. Channel 96 to channel 111"; 264 }; 265 266 constants xmcm_status width(2) "" { 267 XMCM_0 = 0 "All channels enabled without masking (DX is always driven during transmission of data)."; 268 XMCM_1 = 1 "All channels disabled and therefore masked by default. Required channels are selected by enabling XP(A/B)BLK and XCER(A/B) appropriately. Also, these selected channels are not masked and therefore DX is always driven."; 269 XMCM_2 = 2 "All channels enabled, but masked. Selected channels enabled via XP(A/B)BLK and XCER(A/B) are unmasked."; 270 XMCM_3 = 3 "All channels disabled and therefore masked by default. Required channels are selected by enabling RP(A/B)BLK and RCER(A/B) appropriately. Selected channels can be unmasked by RP(A/B)BLK and XCER(A/B). This mode is used for symetric transmit and receive operation."; 271 }; 272 273 register mcbsplp_mcr2_reg addr(base, 0x30) "McBSPLP multi channel register 2" { 274 _ 22 mbz; 275 xmcme 1 rw type(xmcme_status) ""; 276 xpbblk 2 rw type(xpbblk_status) "Transmit Partition B Block (legacy)"; 277 xpablk 2 rw type(xpablk_status) "Transmit Partition A Block (legacy)"; 278 _ 3 mbz; 279 xmcm 2 rw type(xmcm_status) "Transmit Multichannel Selection Enable"; 280 }; 281 282 constants rmcme_status width(1) "" { 283 RMCME_0 = 0 "2-partition mode. Only partitions A and B are used. You can control up to 32 channels in the receive multichannel selection mode (RMCM = 1). Assign 16 channels to partition A with the RPABLK bits. Assign 16 channels to partition B with the RPBBLK bits. You control the channels with the apropriate receive channel enable registers: RCERA: Channels in partition A RCERB: Channels in partition B"; 284 RMCME_1 = 1 "8-partition mode: All partitions (A through H) are used. You can control up to 128 channels in the receive multichannel selection mode. You control the channels with the appropriate receive channel enable registers: RCERA: Channels 0 through 15 RCERB: Channels 16 through 31 RCERC: Channels 32 through 47 RCERD: Channels 48 through 63 RCERE: Channels 64 through 79 RCERF: Channels 80 through 95 RCERG: Channels 96 through 111 RCERH: Channels 112 through 127"; 285 }; 286 287 constants rmcm_status width(1) "" { 288 RMCM_0 = 0 "All 128 channels"; 289 RMCM_1 = 1 "All channels disabled by default. Required channels are selected by enabling RP(A/B)BLK and RCER(A/B) appropriately"; 290 }; 291 292 register mcbsplp_mcr1_reg addr(base, 0x34) "McBSPLP multi channel register 1" { 293 _ 22 mbz; 294 rmcme 1 rw type(rmcme_status) "(legacy)"; 295 rpbblk 2 rw type(xpbblk_status) "Receive Partition B Block (legacy)"; 296 rpablk 2 rw type(xpablk_status) "Receive Partition A Block (legacy)"; 297 _ 4 mbz; 298 rmcm 1 rw type(rmcm_status) "Receive Multichannel Selection Enable"; 299 }; 300 301 register mcbsplp_rcera_reg addr(base, 0x38) "McBSPLP receive channel enable register partition A" { 302 _ 16 mbz; 303 rcera 16 rw "Receive Channel Enable RCERA n=0 Disables reception of n-th channel in an even-numbered block in partition A RCERA n=1 Enables reception of n-th channel in an even-numbered block in partition A"; 304 }; 305 306 register mcbsplp_rcerb_reg addr(base, 0x3C) "McBSPLP receive channel enable register partition B" { 307 _ 16 mbz; 308 rcerb 16 rw "Receive Channel Enable RCERB n=0 Disables reception of n-th channel in a even-numbered block in partition B RCERB n=1 Enables reception of n-th channel in a even-numbered block in partition B"; 309 }; 310 311 register mcbsplp_xcera_reg addr(base, 0x40) "McBSPLP transmit channel enable register partition A" { 312 _ 16 mbz; 313 xcera 16 rw "Transmit Channel Enable XCERA n=0 Disables transmission of n-th channel in an event-numbered block in partition A XCERA n=1 Enables transmission of n-th channel in an event-numbered block in partition A"; 314 }; 315 316 register mcbsplp_xcerb_reg addr(base, 0x44) "McBSPLP transmit channel enable register partition B" { 317 _ 16 mbz; 318 xcerb 16 rw "Transmit Channel Enable XCERB n=0 Disables transmission of n-th channel in an even-numbered block in partition B XCERB n=1 Enables transmission of n-th channel in an even-numbered block in partition B"; 319 }; 320 321 constants idle_en_status width(1) "" { 322 IDLE_EN_0 = 0 "The McBSP is running"; 323 IDLE_EN_1 = 1 "The clocks in the McBSP are shut off when both IDLE_EN=1 and peripheral domain is in idle mode"; 324 }; 325 326 constants xioen_status width(1) "" { 327 XIOEN_0 = 0 "DX, FSX and CLKX are configured as serial port pins and do not function as general-purpose I/Os."; 328 XIOEN_1 = 1 "DX pin is a general purpose output. FSX and CLKX are general purpose I/Os. These serial port pins do not perform serial port operation."; 329 }; 330 331 constants rioen_status width(1) "" { 332 RIOEN_0 = 0 "DR, FSR, CLKR and CLKS are configured as serial port pins and do not function as general-purpose I/Os."; 333 RIOEN_1 = 1 "DR and CLKS pins are general purpose inputs; FSR and CLKR are general purpose I/Os. These serial port pins do not perform serial port operation. The CLKS pin is affected by a combination of RRST and RIOEN signals of the receiver."; 334 }; 335 336 constants fsxm_status width(1) "" { 337 FSXM_0 = 0 "Frame-sync signal derived from an external source"; 338 FSXM_1 = 1 "Frame synchronization is determined by the SRG frame-sync mode bit FSGM in SRGR2."; 339 }; 340 341 constants fsrm_status width(1) "" { 342 FSRM_0 = 0 "Frame-sync pulses generated by an external device. FSR is an input pin."; 343 FSRM_1 = 1 "Frame synchronization generated internally by SRG. FSR is an output pin except when GSYNC=1 in SRGR."; 344 }; 345 346 constants clkxm_status width(1) "" { 347 CLKXM_0 = 0 "Transmitter clock is driven by an external clock with CLKX as an input pin."; 348 CLKXM_1 = 1 "CLKX is an output pin and is driven by the internal sample rate generator."; 349 }; 350 351 constants clkrm_status width(1) "" { 352 CLKRM_0 = 0 "Case 1: Digital loopback mode not set (DLB=0) in SPCR1: Receive clock (CLKR) is an input driven by an externaal clock. Case 2: Digital loopback mode set (DLB=1) in SPCR1: Receive clock (not the CLKR pin) is driven by transmit clock (CLKX) which is based on the CLKXM bit in the PCR. CLKR pin is in high-impedance."; 353 CLKRM_1 = 1 "Case 1: Digital loopback mode not set (DLB=0) in SPCR1: CLKR is an output pin and is driven by the internal SRG. Case 2: Digital loopback mode set (DLB=1) in SPCR1: CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based on the CLKRM bit in the PCR."; 354 }; 355 356 constants sclkme_status width(1) "" { 357 SCLKME_0 = 0 "CLKSM = 0: Signal on CLKS pin CLKSM = 1: CPU clock"; 358 SCLKME_1 = 1 "CLKSM = 0: Signal on CLKR pin CLKSM = 1: Signal on CLKX pin"; 359 }; 360 361 constants clks_stat_status width(1) "" { 362 CLKS_STAT_0_r = 0 "The signal on the CLKS pin is low"; 363 CLKS_STAT_1_r = 1 "The signal on the CLKS pin is high"; 364 }; 365 366 constants dx_stat_status width(1) "" { 367 DX_STAT_0 = 0 "Drive the signal on the DX pin low"; 368 DX_STAT_1 = 1 "Drive the signal on the DX pin high"; 369 }; 370 371 constants dr_stat_status width(1) "" { 372 DR_STAT_0_r = 0 "The signal on DR pin is low"; 373 DR_STAT_1_r = 1 "The signal on DR pin is high"; 374 }; 375 376 constants fsxp_status width(1) "" { 377 FSXP_0 = 0 "Frame-sync pulse FSX is active high"; 378 FSXP_1 = 1 "Frame-sync pulse FSX is active low"; 379 }; 380 381 constants fsrp_status width(1) "" { 382 FSRP_0 = 0 "Frame-sync pulse FSR is active high"; 383 FSRP_1 = 1 "Frame-sync pulse FSR is active low"; 384 }; 385 386 constants clkrp_status width(1) "" { 387 CLKRP_0 = 0 "Receive data sampled on falling edge of CLKR"; 388 CLKRP_1 = 1 "Receive data sampled on rising edge of CLKR"; 389 }; 390 391 register mcbsplp_pcr_reg addr(base, 0x48) "McBSPLP pin control register" { 392 _ 17 mbz; 393 idle_en 1 rw type(idle_en_status) "Idle enable. This bit allows stopping all the clocks in the MCBSPLP. (legacy)"; 394 xioen 1 rw type(xioen_status) "Transmit General Purpose I/O Mode only when XRST=0 in SPCR[1,2] (legacy)"; 395 rioen 1 rw type(rioen_status) "Receive General Purpose I/O Mode when RRST=0 in SPCR[1,2] (legacy)"; 396 fsxm 1 rw type(fsxm_status) "Transmit Frame-Synchronization Mode"; 397 fsrm 1 rw type(fsrm_status) "Receive Frame-Synchronization Mode"; 398 clkxm 1 rw type(clkxm_status) "Transmitter Clock Mode"; 399 clkrm 1 rw type(clkrm_status) "Receiver Clock Mode"; 400 sclkme 1 rw type(sclkme_status) "The frequency of CLKG is: CLKG frequency = (Input clock frequency) / (CLKGDV + 1) SCLKME is used in conjunction with the CLKSM bit to select the input clock:"; 401 clks_stat 1 ro type(clks_stat_status) "CLKS pin status. Reflects value on CLKS pin when selected as a general purpose input. (legacy)"; 402 dx_stat 1 rw type(dx_stat_status) "DX pin status. Reflects value driven on to DX pin when selected as a general purpose output. (legacy)"; 403 dr_stat 1 ro type(dr_stat_status) "DR pin status. Reflects value on DR pin when selected as a general purpose input. (legacy)"; 404 fsxp 1 rw type(fsxp_status) "Transmit Frame-Synchronization Polarity"; 405 fsrp 1 rw type(fsrp_status) "Receive Frame-Synchronization Polarity"; 406 clkxp 1 rw type(clkxm_status) "Transmit Clock Polarity"; 407 clkrp 1 rw type(clkrp_status) "Receive Clock Polarity"; 408 }; 409 410 register mcbsplp_rcerc_reg addr(base, 0x4C) "McBSPLP receive channel enable register partition C" { 411 _ 16 mbz; 412 rcerc 16 rw "Receive Channel Enable RCERC n=0 Disables reception of n-th channel in an even-numbered block in partition C RCERC n=1 Enables reception of n-th channel in an even-numbered block in partition C"; 413 }; 414 415 register mcbsplp_rcerd_reg addr(base, 0x50) "McBSPLP receive channel enable register partition D" { 416 _ 16 mbz; 417 rcerd 16 rw "Receive Channel Enable RCERD n=0 Disables reception of n-th channel in an even-numbered block in partition D RCERD n=1 Enables reception of n-th channel in an even-numbered block in partition D"; 418 }; 419 420 register mcbsplp_xcerc_reg addr(base, 0x54) "McBSPLP transmit channel enable register partition C" { 421 _ 16 mbz; 422 xcerc 16 rw "Transmit Channel Enable XCERC n=0 Disables transmission of n-th channel in an event-numbered block in partition C XCERC n=1 Enables transmission of n-th channel in an event-numbered block in partition C"; 423 }; 424 425 register mcbsplp_xcerd_reg addr(base, 0x58) "McBSPLP transmit channel enable register partition D" { 426 _ 16 mbz; 427 xcerd 16 rw "Transmit Channel Enable XCERD n=0 Disables transmission of n-th channel in an even-numbered block in partition D XCERD n=1 Enables transmission of n-th channel in an even-numbered block in partition D"; 428 }; 429 430 register mcbsplp_rcere_reg addr(base, 0x5C) "McBSPLP receive channel enable register partition E" { 431 _ 16 mbz; 432 rcere 16 rw "Receive Channel Enable RCERE n=0 Disables reception of n-th channel in an even-numbered block in partition E RCERE n=1 Enables reception of n-th channel in an even-numbered block in partition E"; 433 }; 434 435 register mcbsplp_rcerf_reg addr(base, 0x60) "McBSPLP receive channel enable register partition F" { 436 _ 16 mbz; 437 rcerf 16 rw "Receive Channel Enable RCERF n=0 Disables reception of n-th channel in an even-numbered block in partition F RCERF n=1 Enables reception of n-th channel in an even-numbered block in partition F"; 438 }; 439 440 register mcbsplp_xcere_reg addr(base, 0x64) "McBSPLP transmit channel enable register partition E" { 441 _ 16 mbz; 442 xcere 16 rw "Transmit Channel Enable XCERE n=0 Disables transmission of n-th channel in an event-numbered block in partition E XCERE n=1 Enables transmission of n-th channel in an event-numbered block in partition E"; 443 }; 444 445 register mcbsplp_xcerf_reg addr(base, 0x68) "McBSPLP transmit channel enable register partition F" { 446 _ 16 mbz; 447 xcerf 16 rw "Transmit Channel Enable XCERF n=0 Disables transmission of n-th channel in an even-numbered block in partition F XCERF n=1 Enables transmission of n-th channel in an even-numbered block in partition F"; 448 }; 449 450 register mcbsplp_rcerg_reg addr(base, 0x6C) "McBSPLP receive channel enable register partition G" { 451 _ 16 mbz; 452 rcerg 16 rw "Receive Channel Enable RCERG n=0 Disables reception of n-th channel in an even-numbered block in partition G RCERG n=1 Enables reception of n-th channel in an even-numbered block in partition G"; 453 }; 454 455 register mcbsplp_rcerh_reg addr(base, 0x70) "McBSPLP receive channel enable register partition H" { 456 _ 16 mbz; 457 rcerh 16 rw "Receive Channel Enable RCERH n=0 Disables reception of n-th channel in an even-numbered block in partition H RCERH n=1 Enables reception of n-th channel in an even-numbered block in partition H"; 458 }; 459 460 register mcbsplp_xcerg_reg addr(base, 0x74) "McBSPLP transmit channel enable register partition G" { 461 _ 16 mbz; 462 xcerg 16 rw "Transmit Channel Enable XCERG n=0 Disables transmission of n-th channel in an event-numbered block in partition G XCERG n=1 Enables transmission of n-th channel in an event-numbered block in partition G"; 463 }; 464 465 register mcbsplp_xcerh_reg addr(base, 0x78) "McBSPLP transmit channel enable register partition H" { 466 _ 16 mbz; 467 xcerh 16 rw "Transmit Channel Enable XCERH n=0 Disables transmission of n-th channel in an even-numbered block in partition H XCERH n=1 Enables transmission of n-th channel in an even-numbered block in partition H"; 468 }; 469 470 register mcbsplp_rev_reg addr(base, 0x7C) "MCBSPLP Revision number register" { 471 _ 24 mbz; 472 rev 8 ro "Revision number"; 473 }; 474 475 register mcbsplp_rintclr_reg rw addr(base, 0x80) "McBSPLP receive interrupt clear" type(uint32); 476 477 register mcbsplp_xintclr_reg rw addr(base, 0x84) "McBSPLP transmit interrupt clear (legacy)" type(uint32); 478 479 register mcbsplp_rovflclr_reg rw addr(base, 0x88) "McBSPLP receive overflow interrupt clear" type(uint32); 480 481 constants clockactivity_status width(2) "" { 482 CLOCKACTIVITY_0 = 0 "The MCBSPi_ICLK clock can be switched off. The PRCM functional clock can be switched off."; 483 CLOCKACTIVITY_1 = 1 "The MCBSPi_ICLK clock must be maintained during wakeup. The PRCM functional clock can be switched off."; 484 CLOCKACTIVITY_2 = 2 "The MCBSPi_ICLK clock can be switched off. The PRCM functional clock must be maintained during wakeup."; 485 CLOCKACTIVITY_3 = 3 "The MCBSPi_ICLK clock must be maintained during wakeup. The PRCM functional clock must be maintained during wakeup"; 486 }; 487 488 constants sidlemode_status width(2) "" { 489 SIDLEMODE_0 = 0 "Force-idle. An idle request is acknowledged unconditionally."; 490 SIDLEMODE_1 = 1 "No-idle. An idle request is never acknowledged."; 491 SIDLEMODE_2 = 2 "Smart-idle. Acknowledgement to an idle request is given based on the internal activity of the module"; 492 SIDLEMODE_3 = 3 "Reserved"; 493 }; 494 495 constants enawakeup_status width(1) "" { 496 ENAWAKEUP_0 = 0 "WakeUp is disabled"; 497 ENAWAKEUP_1 = 1 "WakeUp capability is enabled"; 498 }; 499 500 constants softreset_status width(1) "" { 501 SOFTRESET_0 = 0 "NO soft reset"; 502 SOFTRESET_1 = 1 "Soft reset triggered"; 503 }; 504 505 register mcbsplp_sysconfig_reg addr(base, 0x8C) "McBSPLP System Configuration register" { 506 _ 22 mbz; 507 clockactivity 2 rw type(clockactivity_status) ""; 508 _ 3 mbz; 509 sidlemode 2 rw type(sidlemode_status) "Slave interface power management, req/ack control:"; 510 enawakeup 1 rw type(enawakeup_status) "WakeUp feature control:"; 511 softreset 1 rw type(softreset_status) "McBSPLP global software reset"; 512 _ 1 mbz; 513 }; 514 515 register mcbsplp_thrsh2_reg addr(base, 0x90) "McBSPLP transmit buffer threshold (DMA or IRQ trigger)" { 516 _ 25 mbz; 517 xthreshold 7 rw "Transmit buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of free locations inside transmit buffer are above or equal to the XTHRESHOLD value + 1. Also, this value (XTHRESHOLD value + 1) indicates the number of words transferred during a transmit data DMA request, if transmit DMA is enabled"; 518 }; 519 520 register mcbsplp_thrsh1_reg addr(base, 0x94) "McBSPLP receive buffer threshold (DMA or IRQ trigger)" { 521 _ 25 mbz; 522 rthreshold 7 rw "Receive buffer threshold value. The DMA request (if enabled) of interrupt assertion (if enabled) will be triggered if the number of occupied locations inside receive buffer are above or equal to the RTHRESHOLD value + 1. Also, this value (RTHRESHOLD value + 1) indicates the number of words transferred during a receive data DMA request, if receive DMA is enabled."; 523 }; 524 525 constants xemptyeof_status width(1) "" { 526 XEMPTYEOF_0 = 0 "XEMPTYEOF is NOT set to when a complete frame was transmitted and the transmit buffer is empty"; 527 XEMPTYEOF_1 = 1 "XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty. Writing 1 to this bit clears the bit."; 528 }; 529 530 constants xovflstat_status width(1) "" { 531 XOVFLSTAT_0 = 0 "Transmit buffer NOT overflow"; 532 XOVFLSTAT_1 = 1 "Transmit buffer overflow; Writing 1 to this bit clears the bit."; 533 }; 534 535 constants xundflstat_status width(1) "" { 536 XUNDFLSTAT_0 = 0 "the transmit data buffer is NOT empty new data is required to be transmitted."; 537 XUNDFLSTAT_1 = 1 "the transmit data buffer is empty new data is required to be transmitted. Writing 1 to this bit clears the bit."; 538 }; 539 540 constants xrdy_status1 width(1) "" { 541 XRDY_0 = 0 "Transmit buffer occupied locations are below the THRSH2_REG value)."; 542 XRDY_1 = 1 "Transmit buffer occupied locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit."; 543 }; 544 545 constants xeof_status width(1) "" { 546 XEOF_0 = 0 "complete frame was NOT transmitted"; 547 XEOF_1 = 1 "complete frame was transmitted; Writing 1 to this bit clears the bit."; 548 }; 549 550 constants rovflstat_status width(1) "" { 551 ROVFLSTAT_0 = 0 "receive buffer NOT overflow"; 552 ROVFLSTAT_1 = 1 "receive buffer overflow; Writing 1 to this bit clears the bit."; 553 }; 554 555 constants rrdy_status1 width(1) "" { 556 RRDY_0 = 0 "receive buffer occupied locations are below the THRSH1_REG value)."; 557 RRDY_1 = 1 "receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit."; 558 }; 559 560 constants reof_status width(1) "" { 561 REOF_0 = 0 "complete frame was NOT received"; 562 REOF_1 = 1 "complete frame was received; Writing 1 to this bit clears the bit."; 563 }; 564 565 register mcbsplp_irqstatus_reg addr(base, 0xA0) "McBSPLP Interrupt Status register (interconnect compliant IRQ line)" { 566 _ 17 mbz; 567 xemptyeof 1 rw type(xemptyeof_status) "Transmit Buffer Empty at end of frame (XEMPTYEOF is set to 1 when a complete frame was transmitted and the transmit buffer is empty)."; 568 _ 1 mbz; 569 xovflstat 1 rw type(xovflstat_status) "Transmit Buffer Overflow (XOVFLSTAT bit is set to 1 when transmit buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit."; 570 xundflstat 1 rw type(xundflstat_status) "Transmit Buffer Underflow (XUNDFLSTAT bit is set to 1 when the transmit data buffer is empty new data is required to be transmitted). Writing 1 to this bit clears the bit."; 571 xrdy 1 rw type(xrdy_status1) "Transmit Buffer Threshold Reached (XRDY bit is set to 1 when the transmit buffer free locations are equal or above the THRSH2_REG value). Writing 1 to this bit clears the bit."; 572 xeof 1 rw type(xeof_status) "Transmit End Of Frame (XEOF is set to 1 when a complete frame was transmitted). Writing 1 to this bit clears the bit."; 573 xfsx 1 rw type(xundflstat_status) "Transmit Frame Synchronization (XFSX bit is set to 1 when a new transmit frame synchronization is asserted). Writing 1 to this bit clears the bit."; 574 xsyncerr 1 rw type(xundflstat_status) "Transmit Frame Synchronization Error (XSYNCERR is set to 1 when a transmit frame-sync error is detected). Writing 1 to this bit clears the bit."; 575 _ 1 mbz; 576 rovflstat 1 rw type(rovflstat_status) "Receive Buffer Overflow (ROVFLSTAT bit is set to 1 when receive buffer overflow; the data which is written while overflow condition is discarded). Writing 1 to this bit clears the bit."; 577 rundflstat 1 rw type(xundflstat_status) "Receive Buffer Underflow (RUNDFLSTAT bit is set to 1 when read operation is performed to the receive data register while receive buffer is empty; data read while underflow condition is undefined). Writing 1 to this bit clears the bit."; 578 rrdy 1 rw type(rrdy_status1) "Receive Buffer Threshold Reached (RRDY bit is set to 1 when the receive buffer occupied locations are equal or above the THRSH1_REG value). Writing 1 to this bit clears the bit."; 579 reof 1 rw type(reof_status) "Receive End Of Frame (REOF is set to 1 when a complete frame was received). Writing 1 to this bit clears the bit."; 580 rfsr 1 rw type(xundflstat_status) "Receive Frame Synchronization (RFSR bit is set to 1 when a new receive frame synchronization is asserted). Writing 1 to this bit clears the bit."; 581 rsyncerr 1 rw type(xundflstat_status) "Receive Frame Synchronization Error (RSYNCERR is set to 1 when a receive frame-sync error is detected). Writing 1 to this bit clears the bit."; 582 }; 583 584 constants xovflen_status width(1) "" { 585 XOVFLEN_0 = 0 "Transmit Buffer Overflow NOT enabled"; 586 XOVFLEN_1 = 1 "Transmit Buffer Overflow enabled"; 587 }; 588 589 constants xundflen_status width(1) "" { 590 XUNDFLEN_0 = 0 "Transmit Buffer Underflow NOT enabled"; 591 XUNDFLEN_1 = 1 "Transmit Buffer Underflow enabled"; 592 }; 593 594 constants xeofen_status width(1) "" { 595 XEOFEN_0 = 0 "Transmit End Of Frame NOT enabled"; 596 XEOFEN_1 = 1 "Transmit End Of Frame enabled"; 597 }; 598 599 constants xfsxen_status width(1) "" { 600 XFSXEN_0 = 0 "Transmit Frame Synchronization NOT enabled"; 601 XFSXEN_1 = 1 "Transmit Frame Synchronization enabled"; 602 }; 603 604 constants rovflen_status width(1) "" { 605 ROVFLEN_0 = 0 "Receive Buffer Overflow NOT enabled"; 606 ROVFLEN_1 = 1 "Receive Buffer Overflow enabled"; 607 }; 608 609 constants rundflen_status width(1) "" { 610 RUNDFLEN_0 = 0 "Receive Buffer Underflow NOT enabled"; 611 RUNDFLEN_1 = 1 "Receive Buffer Underflow enabled"; 612 }; 613 614 constants rrdyen_status width(1) "" { 615 RRDYEN_0 = 0 "Receive Buffer Threshold NOT enabled"; 616 RRDYEN_1 = 1 "Receive Buffer Threshold enabled"; 617 }; 618 619 constants reofen_status width(1) "" { 620 REOFEN_0 = 0 "Receive End Of Frame NOT enabled"; 621 REOFEN_1 = 1 "Receive End Of Frame enabled"; 622 }; 623 624 constants rfsren_status width(1) "" { 625 RFSREN_0 = 0 "Receive Frame Synchronization NOT enabled"; 626 RFSREN_1 = 1 "Receive Frame Synchronization enabled"; 627 }; 628 629 register mcbsplp_irqenable_reg addr(base, 0xA4) "McBSPLP Interrupt Enable register (interconnect compliant IRQ line)" { 630 _ 17 mbz; 631 xemptyeofen 1 rw type(xundflstat_status) "Transmit buffer empty at end of frame enable bit."; 632 _ 1 mbz; 633 xovflen 1 rw type(xovflen_status) "Transmit Buffer Overflow enable bit."; 634 xundflen 1 rw type(xundflen_status) "Transmit Buffer Underflow enable bit."; 635 xrdyen 1 rw type(xundflstat_status) "Transmit Buffer Threshold Reached enable bit."; 636 xeofen 1 rw type(xeofen_status) "Transmit End Of Frame enable bit."; 637 xfsxen 1 rw type(xfsxen_status) "Transmit Frame Synchronization enable bit."; 638 xsyncerren 1 rw type(xundflstat_status) "Transmit Frame Synchronization Error enable bit."; 639 _ 1 mbz; 640 rovflen 1 rw type(rovflen_status) "Receive Buffer Overflow enable bit."; 641 rundflen 1 rw type(rundflen_status) "Receive Buffer Underflow enable bit."; 642 rrdyen 1 rw type(rrdyen_status) "Receive Buffer Threshold enable bit."; 643 reofen 1 rw type(reofen_status) "Receive End Of Frame enable bit."; 644 rfsren 1 rw type(rfsren_status) "Receive Frame Synchronization enable bit. RW"; 645 rsyncerren 1 rw type(xundflstat_status) "Receive Frame Synchronization Error enable bit."; 646 }; 647 648 constants xemptyeofen_status width(1) "" { 649 XEMPTYEOFEN_0_1 = 0 "Transmit Buffer Empty at End Of Frame WK enable is NOT active"; 650 XEMPTYEOFEN_1_1 = 1 "Transmit Buffer Empty at End Of Frame WK enable is active"; 651 }; 652 653 register mcbsplp_wakeupen_reg addr(base, 0xA8) "McBSPLP Wakeup Enable register" { 654 _ 17 mbz; 655 xemptyeofen 1 rw type(xemptyeofen_status) "Transmit Buffer Empty at End Of Frame enable bit."; 656 _ 3 mbz; 657 xrdyen 1 rw type(xemptyeofen_status) "Transmit Buffer Threshold Reached WK enable bit."; 658 xeofen 1 rw type(xemptyeofen_status) "Transmit End Of Frame WK enable bit."; 659 xfsxen 1 rw type(xemptyeofen_status) "Transmit Frame Synchronization WK enable bit."; 660 xsyncerren 1 rw type(xemptyeofen_status) "Transmit Frame Synchronization Error WK enable bit."; 661 _ 3 mbz; 662 rrdyen 1 rw type(xemptyeofen_status) "Receive Buffer Threshold wakeup enable bit."; 663 reofen 1 rw type(xemptyeofen_status) "Receive End Of Frame WK enable bit."; 664 rfsren 1 rw type(xemptyeofen_status) "Receive Frame Synchronization WK enable bit."; 665 rsyncerren 1 rw type(xemptyeofen_status) "Receive Frame Synchronization Error WK enable bit."; 666 }; 667 668 constants extclkgate_status width(1) "" { 669 EXTCLKGATE_0 = 0 "External clock gating disabled."; 670 EXTCLKGATE_1 = 1 "External clock gating enable."; 671 }; 672 673 constants ppconnect_status width(1) "" { 674 PPCONNECT_0 = 0 "Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output"; 675 PPCONNECT_1 = 1 "Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output"; 676 }; 677 678 constants dxendly_status width(2) "" { 679 DXENDLY_0 = 0 "80 ps"; 680 DXENDLY_1 = 1 "160 ps (default)"; 681 DXENDLY_2 = 2 "240 ps"; 682 DXENDLY_3 = 3 "320 ps"; 683 }; 684 685 constants dlb_status width(1) "" { 686 DLB_0 = 0 "No DLB"; 687 DLB_1 = 1 "DLB"; 688 }; 689 690 constants xdmaen_status width(1) "" { 691 XDMAEN_0 = 0 "When set to 0 this bit will gate the external transmit DMA request,"; 692 XDMAEN_1 = 1 "When set to 1 this bit will NOT gate the external transmit DMA request,"; 693 }; 694 695 register mcbsplp_xccr_reg addr(base, 0xAC) "McBSPLP transmit configuration control register" { 696 _ 16 mbz; 697 extclkgate 1 rw type(extclkgate_status) "External clock gating enable (CLKX and FSX master only). When this bit is set and the transmit clock and FSX are set as output, the CLKX is enabled when FSX is active plus 3 clock cycles after (clock is provided for FWID + 4 clock cycles, assuming that the FSX width, active, is FWID + 1 clock cycles); outside this window the external transmit clock is gated. The receive use the same gated transmit clock and transmit frame synchronization signals regardless of the CLKRM/FSRM settings. When using this mode the frame synchronization signal must be active during reception of the entire frame (FWID must be programmed accordingly) to ensure the proper receive process, which requires at least 3 cycles after the frame complete to transfer the data into the receive buffer."; 698 ppconnect 1 rw type(ppconnect_status) "Pair to pair connection. When set the DXENO pin is always set to 0 regardless of the frame boundary, setting the tree state buffer as output"; 699 dxendly 2 rw type(dxendly_status) "When DXENA bit in SPCR1 is set to 1 this field selects the added delay as follow:"; 700 xfull_cycle 1 rw type(sidlemode_status) "Transmit full-cycle mode select."; 701 _ 5 mbz; 702 dlb 1 rw type(dlb_status) "Digital Loop-Back"; 703 _ 1 mbz; 704 xdmaen 1 rw type(xdmaen_status) "Transmit DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during transmit reset."; 705 _ 2 mbz; 706 xdisable 1 rw type(xundflstat_status) "Transmit Disable bit. When this bit is set the transmit process will stop at the next frame boundary."; 707 }; 708 709 register mcbsplp_rccr_reg addr(base, 0xB0) "McBSPLP receive configuration control register" { 710 _ 20 mbz; 711 rfull_cycle 1 rw type(sidlemode_status) "Receive full-cycle mode select."; 712 _ 7 mbz; 713 rdmaen 1 rw type(xdmaen_status) "Receive DMA Enable bit. When set to 0 this bit will gate the external transmit DMA request, without resetting the DMA state machine. It is recommended to change this bit value only during receive reset."; 714 _ 2 mbz; 715 rdisable 1 rw type(xundflstat_status) "Receive Disable bit. When this bit is set the receive process will stop at the next frame boundary."; 716 }; 717 718 register mcbsplp_xbuffstat_reg addr(base, 0xB4) "McBSPLP transmit buffer status" { 719 _ 24 mbz; 720 xbuffstat 8 ro "Transmit Buffer Status (indicates the number of free locations inside transmit buffer). The XBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the number of free locations which are seen by the transmit state machine."; 721 }; 722 723 register mcbsplp_rbuffstat_reg addr(base, 0xB8) "McBSPLP receive buffer status" { 724 _ 24 mbz; 725 rbuffstat 8 ro "Receive Buffer Status (indicates the number of occupied locations inside receive buffer). The RBUFFSTAT value reflects the buffer status on the interface clock domain and it can be smaller than the real number of the occupied locations which are seen by the receive state machine."; 726 }; 727};