1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_ma_firewall.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_ma_firewall msbfirst ( addr base ) "" { 29 30 31 register error_log_k_0 addr(base, 0x0) "Error log register for port k" { 32 _ 8 mbz; 33 blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 34 _ 1 mbz; 35 region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 36 region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 37 reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 38 }; 39 40 register error_log_k_1 addr(base, 0x10) "Error log register for port k" { 41 _ 8 mbz; 42 blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 43 _ 1 mbz; 44 region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 45 region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 46 reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 47 }; 48 49 register error_log_k_2 addr(base, 0x20) "Error log register for port k" { 50 _ 8 mbz; 51 blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 52 _ 1 mbz; 53 region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 54 region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 55 reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 56 }; 57 58 register logical_addr_errlog_k_0 ro addr(base, 0x4) "Logical Physical Address Error log register for port k" type(uint32); 59 60 register logical_addr_errlog_k_1 ro addr(base, 0x14) "Logical Physical Address Error log register for port k" type(uint32); 61 62 register logical_addr_errlog_k_2 ro addr(base, 0x24) "Logical Physical Address Error log register for port k" type(uint32); 63 64 register regupdate_control addr(base, 0x40) "Register update control register" { 65 _ 30 mbz; 66 fw_load_req 1 ro "Hadrdware set/Software clear"; 67 busy_req 1 rw "Busy request"; 68 }; 69 70 register start_region_i_1 addr(base, 0x90) "Start physical address of region i" { 71 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 72 _ 12 mbz; 73 }; 74 75 register start_region_i_2 addr(base, 0xA0) "Start physical address of region i" { 76 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 77 _ 12 mbz; 78 }; 79 80 register start_region_i_3 addr(base, 0xB0) "Start physical address of region i" { 81 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 82 _ 12 mbz; 83 }; 84 85 register start_region_i_4 addr(base, 0xC0) "Start physical address of region i" { 86 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 87 _ 12 mbz; 88 }; 89 90 register start_region_i_5 addr(base, 0xD0) "Start physical address of region i" { 91 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 92 _ 12 mbz; 93 }; 94 95 register start_region_i_6 addr(base, 0xE0) "Start physical address of region i" { 96 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 97 _ 12 mbz; 98 }; 99 100 register start_region_i_7 addr(base, 0xF0) "Start physical address of region i" { 101 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 102 _ 12 mbz; 103 }; 104 105 register end_region_i_1 addr(base, 0x94) "End physical address of region i" { 106 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 107 _ 9 mbz; 108 region_enable_port2 1 rw "Enable this region for port 2."; 109 region_enable_port1 1 rw "Enable this region for port 1."; 110 region_enable_port0 1 rw "Enable this region for port 0."; 111 }; 112 113 register end_region_i_2 addr(base, 0xA4) "End physical address of region i" { 114 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 115 _ 9 mbz; 116 region_enable_port2 1 rw "Enable this region for port 2."; 117 region_enable_port1 1 rw "Enable this region for port 1."; 118 region_enable_port0 1 rw "Enable this region for port 0."; 119 }; 120 121 register end_region_i_3 addr(base, 0xB4) "End physical address of region i" { 122 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 123 _ 9 mbz; 124 region_enable_port2 1 rw "Enable this region for port 2."; 125 region_enable_port1 1 rw "Enable this region for port 1."; 126 region_enable_port0 1 rw "Enable this region for port 0."; 127 }; 128 129 register end_region_i_4 addr(base, 0xC4) "End physical address of region i" { 130 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 131 _ 9 mbz; 132 region_enable_port2 1 rw "Enable this region for port 2."; 133 region_enable_port1 1 rw "Enable this region for port 1."; 134 region_enable_port0 1 rw "Enable this region for port 0."; 135 }; 136 137 register end_region_i_5 addr(base, 0xD4) "End physical address of region i" { 138 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 139 _ 9 mbz; 140 region_enable_port2 1 rw "Enable this region for port 2."; 141 region_enable_port1 1 rw "Enable this region for port 1."; 142 region_enable_port0 1 rw "Enable this region for port 0."; 143 }; 144 145 register end_region_i_6 addr(base, 0xE4) "End physical address of region i" { 146 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 147 _ 9 mbz; 148 region_enable_port2 1 rw "Enable this region for port 2."; 149 region_enable_port1 1 rw "Enable this region for port 1."; 150 region_enable_port0 1 rw "Enable this region for port 0."; 151 }; 152 153 register end_region_i_7 addr(base, 0xF4) "End physical address of region i" { 154 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 155 _ 9 mbz; 156 region_enable_port2 1 rw "Enable this region for port 2."; 157 region_enable_port1 1 rw "Enable this region for port 1."; 158 region_enable_port0 1 rw "Enable this region for port 0."; 159 }; 160 161 register mrm_permission_region_low_j_0 addr(base, 0x88) "Region j Permission Low" { 162 _ 1 rsvd; 163 _ 1 rsvd; 164 _ 1 rsvd; 165 _ 1 rsvd; 166 _ 1 rsvd; 167 _ 1 rsvd; 168 _ 1 rsvd; 169 _ 1 rsvd; 170 _ 1 rsvd; 171 _ 1 rsvd; 172 _ 1 rsvd; 173 _ 1 rsvd; 174 _ 1 rsvd; 175 _ 1 rsvd; 176 _ 1 rsvd; 177 _ 1 rsvd; 178 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 179 pub_usr_debug 1 rw "Public User Debug Allowed"; 180 _ 1 rsvd; 181 _ 1 rsvd; 182 pub_prv_write 1 rw "Public Privilege Write Allowed"; 183 pub_prv_read 1 rw "Public Privilege Read Allowed"; 184 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 185 pub_usr_write 1 rw "Public User Write Access Allowed"; 186 pub_usr_read 1 rw "Public User Read Access Allowed"; 187 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 188 _ 1 rsvd; 189 _ 1 rsvd; 190 _ 1 rsvd; 191 _ 1 rsvd; 192 _ 1 rsvd; 193 _ 1 rsvd; 194 }; 195 196 register mrm_permission_region_low_j_1 addr(base, 0x98) "Region j Permission Low" { 197 _ 1 rsvd; 198 _ 1 rsvd; 199 _ 1 rsvd; 200 _ 1 rsvd; 201 _ 1 rsvd; 202 _ 1 rsvd; 203 _ 1 rsvd; 204 _ 1 rsvd; 205 _ 1 rsvd; 206 _ 1 rsvd; 207 _ 1 rsvd; 208 _ 1 rsvd; 209 _ 1 rsvd; 210 _ 1 rsvd; 211 _ 1 rsvd; 212 _ 1 rsvd; 213 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 214 pub_usr_debug 1 rw "Public User Debug Allowed"; 215 _ 1 rsvd; 216 _ 1 rsvd; 217 pub_prv_write 1 rw "Public Privilege Write Allowed"; 218 pub_prv_read 1 rw "Public Privilege Read Allowed"; 219 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 220 pub_usr_write 1 rw "Public User Write Access Allowed"; 221 pub_usr_read 1 rw "Public User Read Access Allowed"; 222 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 223 _ 1 rsvd; 224 _ 1 rsvd; 225 _ 1 rsvd; 226 _ 1 rsvd; 227 _ 1 rsvd; 228 _ 1 rsvd; 229 }; 230 231 register mrm_permission_region_low_j_2 addr(base, 0xA8) "Region j Permission Low" { 232 _ 1 rsvd; 233 _ 1 rsvd; 234 _ 1 rsvd; 235 _ 1 rsvd; 236 _ 1 rsvd; 237 _ 1 rsvd; 238 _ 1 rsvd; 239 _ 1 rsvd; 240 _ 1 rsvd; 241 _ 1 rsvd; 242 _ 1 rsvd; 243 _ 1 rsvd; 244 _ 1 rsvd; 245 _ 1 rsvd; 246 _ 1 rsvd; 247 _ 1 rsvd; 248 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 249 pub_usr_debug 1 rw "Public User Debug Allowed"; 250 _ 1 rsvd; 251 _ 1 rsvd; 252 pub_prv_write 1 rw "Public Privilege Write Allowed"; 253 pub_prv_read 1 rw "Public Privilege Read Allowed"; 254 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 255 pub_usr_write 1 rw "Public User Write Access Allowed"; 256 pub_usr_read 1 rw "Public User Read Access Allowed"; 257 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 258 _ 1 rsvd; 259 _ 1 rsvd; 260 _ 1 rsvd; 261 _ 1 rsvd; 262 _ 1 rsvd; 263 _ 1 rsvd; 264 }; 265 266 register mrm_permission_region_low_j_3 addr(base, 0xB8) "Region j Permission Low" { 267 _ 1 rsvd; 268 _ 1 rsvd; 269 _ 1 rsvd; 270 _ 1 rsvd; 271 _ 1 rsvd; 272 _ 1 rsvd; 273 _ 1 rsvd; 274 _ 1 rsvd; 275 _ 1 rsvd; 276 _ 1 rsvd; 277 _ 1 rsvd; 278 _ 1 rsvd; 279 _ 1 rsvd; 280 _ 1 rsvd; 281 _ 1 rsvd; 282 _ 1 rsvd; 283 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 284 pub_usr_debug 1 rw "Public User Debug Allowed"; 285 _ 1 rsvd; 286 _ 1 rsvd; 287 pub_prv_write 1 rw "Public Privilege Write Allowed"; 288 pub_prv_read 1 rw "Public Privilege Read Allowed"; 289 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 290 pub_usr_write 1 rw "Public User Write Access Allowed"; 291 pub_usr_read 1 rw "Public User Read Access Allowed"; 292 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 293 _ 1 rsvd; 294 _ 1 rsvd; 295 _ 1 rsvd; 296 _ 1 rsvd; 297 _ 1 rsvd; 298 _ 1 rsvd; 299 }; 300 301 register mrm_permission_region_low_j_4 addr(base, 0xC8) "Region j Permission Low" { 302 _ 1 rsvd; 303 _ 1 rsvd; 304 _ 1 rsvd; 305 _ 1 rsvd; 306 _ 1 rsvd; 307 _ 1 rsvd; 308 _ 1 rsvd; 309 _ 1 rsvd; 310 _ 1 rsvd; 311 _ 1 rsvd; 312 _ 1 rsvd; 313 _ 1 rsvd; 314 _ 1 rsvd; 315 _ 1 rsvd; 316 _ 1 rsvd; 317 _ 1 rsvd; 318 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 319 pub_usr_debug 1 rw "Public User Debug Allowed"; 320 _ 1 rsvd; 321 _ 1 rsvd; 322 pub_prv_write 1 rw "Public Privilege Write Allowed"; 323 pub_prv_read 1 rw "Public Privilege Read Allowed"; 324 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 325 pub_usr_write 1 rw "Public User Write Access Allowed"; 326 pub_usr_read 1 rw "Public User Read Access Allowed"; 327 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 328 _ 1 rsvd; 329 _ 1 rsvd; 330 _ 1 rsvd; 331 _ 1 rsvd; 332 _ 1 rsvd; 333 _ 1 rsvd; 334 }; 335 336 register mrm_permission_region_low_j_5 addr(base, 0xD8) "Region j Permission Low" { 337 _ 1 rsvd; 338 _ 1 rsvd; 339 _ 1 rsvd; 340 _ 1 rsvd; 341 _ 1 rsvd; 342 _ 1 rsvd; 343 _ 1 rsvd; 344 _ 1 rsvd; 345 _ 1 rsvd; 346 _ 1 rsvd; 347 _ 1 rsvd; 348 _ 1 rsvd; 349 _ 1 rsvd; 350 _ 1 rsvd; 351 _ 1 rsvd; 352 _ 1 rsvd; 353 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 354 pub_usr_debug 1 rw "Public User Debug Allowed"; 355 _ 1 rsvd; 356 _ 1 rsvd; 357 pub_prv_write 1 rw "Public Privilege Write Allowed"; 358 pub_prv_read 1 rw "Public Privilege Read Allowed"; 359 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 360 pub_usr_write 1 rw "Public User Write Access Allowed"; 361 pub_usr_read 1 rw "Public User Read Access Allowed"; 362 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 363 _ 1 rsvd; 364 _ 1 rsvd; 365 _ 1 rsvd; 366 _ 1 rsvd; 367 _ 1 rsvd; 368 _ 1 rsvd; 369 }; 370 371 register mrm_permission_region_low_j_6 addr(base, 0xE8) "Region j Permission Low" { 372 _ 1 rsvd; 373 _ 1 rsvd; 374 _ 1 rsvd; 375 _ 1 rsvd; 376 _ 1 rsvd; 377 _ 1 rsvd; 378 _ 1 rsvd; 379 _ 1 rsvd; 380 _ 1 rsvd; 381 _ 1 rsvd; 382 _ 1 rsvd; 383 _ 1 rsvd; 384 _ 1 rsvd; 385 _ 1 rsvd; 386 _ 1 rsvd; 387 _ 1 rsvd; 388 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 389 pub_usr_debug 1 rw "Public User Debug Allowed"; 390 _ 1 rsvd; 391 _ 1 rsvd; 392 pub_prv_write 1 rw "Public Privilege Write Allowed"; 393 pub_prv_read 1 rw "Public Privilege Read Allowed"; 394 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 395 pub_usr_write 1 rw "Public User Write Access Allowed"; 396 pub_usr_read 1 rw "Public User Read Access Allowed"; 397 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 398 _ 1 rsvd; 399 _ 1 rsvd; 400 _ 1 rsvd; 401 _ 1 rsvd; 402 _ 1 rsvd; 403 _ 1 rsvd; 404 }; 405 406 register mrm_permission_region_low_j_7 addr(base, 0xF8) "Region j Permission Low" { 407 _ 1 rsvd; 408 _ 1 rsvd; 409 _ 1 rsvd; 410 _ 1 rsvd; 411 _ 1 rsvd; 412 _ 1 rsvd; 413 _ 1 rsvd; 414 _ 1 rsvd; 415 _ 1 rsvd; 416 _ 1 rsvd; 417 _ 1 rsvd; 418 _ 1 rsvd; 419 _ 1 rsvd; 420 _ 1 rsvd; 421 _ 1 rsvd; 422 _ 1 rsvd; 423 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 424 pub_usr_debug 1 rw "Public User Debug Allowed"; 425 _ 1 rsvd; 426 _ 1 rsvd; 427 pub_prv_write 1 rw "Public Privilege Write Allowed"; 428 pub_prv_read 1 rw "Public Privilege Read Allowed"; 429 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 430 pub_usr_write 1 rw "Public User Write Access Allowed"; 431 pub_usr_read 1 rw "Public User Read Access Allowed"; 432 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 433 _ 1 rsvd; 434 _ 1 rsvd; 435 _ 1 rsvd; 436 _ 1 rsvd; 437 _ 1 rsvd; 438 _ 1 rsvd; 439 }; 440 441 register mrm_permission_region_high_j_0 addr(base, 0x8C) "Region j Permission High" { 442 _ 6 rsvd; 443 w12 1 rw "Master NIU ConnID = 12 write permission"; 444 r12 1 rw "Master NIU ConnID = 12 read permission"; 445 _ 1 rsvd; 446 _ 1 rsvd; 447 w10 1 rw "Master NIU ConnID = 10 write permission"; 448 r10 1 rw "Master NIU ConnID = 10 read permission"; 449 w9 1 rw "Master NIU ConnID = 9 write permission"; 450 r9 1 rw "Master NIU ConnID = 9 read permission"; 451 w8 1 rw "Master NIU ConnID = 8 write permission"; 452 r8 1 rw "Master NIU ConnID = 8 read permission"; 453 w7 1 rw "Master NIU ConnID = 7 write permission"; 454 r7 1 rw "Master NIU ConnID = 7 read permission"; 455 w6 1 rw "Master NIU ConnID = 6 write permission"; 456 r6 1 rw "Master NIU ConnID = 6 read permission"; 457 w5 1 rw "Master NIU ConnID = 5 write permission"; 458 r5 1 rw "Master NIU ConnID = 5 read permission"; 459 w4 1 rw "Master NIU ConnID = 4 write permission"; 460 r4 1 rw "Master NIU ConnID = 4 read permission"; 461 w3 1 rw "Master NIU ConnID = 3 write permission"; 462 r3 1 rw "Master NIU ConnID = 3 read permission"; 463 w2 1 rw "Master NIU ConnID = 2 write permission"; 464 r2 1 rw "Master NIU ConnID = 2 read permission"; 465 w1 1 rw "Master NIU ConnID = 1 write permission"; 466 r1 1 rw "Master NIU ConnID = 1 read permission"; 467 w0 1 rw "Master NIU ConnID = 0 write permission"; 468 r0 1 rw "Master NIU ConnID = 0 read permission"; 469 }; 470 471 register mrm_permission_region_high_j_1 addr(base, 0x9C) "Region j Permission High" { 472 _ 6 rsvd; 473 w12 1 rw "Master NIU ConnID = 12 write permission"; 474 r12 1 rw "Master NIU ConnID = 12 read permission"; 475 _ 1 rsvd; 476 _ 1 rsvd; 477 w10 1 rw "Master NIU ConnID = 10 write permission"; 478 r10 1 rw "Master NIU ConnID = 10 read permission"; 479 w9 1 rw "Master NIU ConnID = 9 write permission"; 480 r9 1 rw "Master NIU ConnID = 9 read permission"; 481 w8 1 rw "Master NIU ConnID = 8 write permission"; 482 r8 1 rw "Master NIU ConnID = 8 read permission"; 483 w7 1 rw "Master NIU ConnID = 7 write permission"; 484 r7 1 rw "Master NIU ConnID = 7 read permission"; 485 w6 1 rw "Master NIU ConnID = 6 write permission"; 486 r6 1 rw "Master NIU ConnID = 6 read permission"; 487 w5 1 rw "Master NIU ConnID = 5 write permission"; 488 r5 1 rw "Master NIU ConnID = 5 read permission"; 489 w4 1 rw "Master NIU ConnID = 4 write permission"; 490 r4 1 rw "Master NIU ConnID = 4 read permission"; 491 w3 1 rw "Master NIU ConnID = 3 write permission"; 492 r3 1 rw "Master NIU ConnID = 3 read permission"; 493 w2 1 rw "Master NIU ConnID = 2 write permission"; 494 r2 1 rw "Master NIU ConnID = 2 read permission"; 495 w1 1 rw "Master NIU ConnID = 1 write permission"; 496 r1 1 rw "Master NIU ConnID = 1 read permission"; 497 w0 1 rw "Master NIU ConnID = 0 write permission"; 498 r0 1 rw "Master NIU ConnID = 0 read permission"; 499 }; 500 501 register mrm_permission_region_high_j_2 addr(base, 0xAC) "Region j Permission High" { 502 _ 6 rsvd; 503 w12 1 rw "Master NIU ConnID = 12 write permission"; 504 r12 1 rw "Master NIU ConnID = 12 read permission"; 505 _ 1 rsvd; 506 _ 1 rsvd; 507 w10 1 rw "Master NIU ConnID = 10 write permission"; 508 r10 1 rw "Master NIU ConnID = 10 read permission"; 509 w9 1 rw "Master NIU ConnID = 9 write permission"; 510 r9 1 rw "Master NIU ConnID = 9 read permission"; 511 w8 1 rw "Master NIU ConnID = 8 write permission"; 512 r8 1 rw "Master NIU ConnID = 8 read permission"; 513 w7 1 rw "Master NIU ConnID = 7 write permission"; 514 r7 1 rw "Master NIU ConnID = 7 read permission"; 515 w6 1 rw "Master NIU ConnID = 6 write permission"; 516 r6 1 rw "Master NIU ConnID = 6 read permission"; 517 w5 1 rw "Master NIU ConnID = 5 write permission"; 518 r5 1 rw "Master NIU ConnID = 5 read permission"; 519 w4 1 rw "Master NIU ConnID = 4 write permission"; 520 r4 1 rw "Master NIU ConnID = 4 read permission"; 521 w3 1 rw "Master NIU ConnID = 3 write permission"; 522 r3 1 rw "Master NIU ConnID = 3 read permission"; 523 w2 1 rw "Master NIU ConnID = 2 write permission"; 524 r2 1 rw "Master NIU ConnID = 2 read permission"; 525 w1 1 rw "Master NIU ConnID = 1 write permission"; 526 r1 1 rw "Master NIU ConnID = 1 read permission"; 527 w0 1 rw "Master NIU ConnID = 0 write permission"; 528 r0 1 rw "Master NIU ConnID = 0 read permission"; 529 }; 530 531 register mrm_permission_region_high_j_3 addr(base, 0xBC) "Region j Permission High" { 532 _ 6 rsvd; 533 w12 1 rw "Master NIU ConnID = 12 write permission"; 534 r12 1 rw "Master NIU ConnID = 12 read permission"; 535 _ 1 rsvd; 536 _ 1 rsvd; 537 w10 1 rw "Master NIU ConnID = 10 write permission"; 538 r10 1 rw "Master NIU ConnID = 10 read permission"; 539 w9 1 rw "Master NIU ConnID = 9 write permission"; 540 r9 1 rw "Master NIU ConnID = 9 read permission"; 541 w8 1 rw "Master NIU ConnID = 8 write permission"; 542 r8 1 rw "Master NIU ConnID = 8 read permission"; 543 w7 1 rw "Master NIU ConnID = 7 write permission"; 544 r7 1 rw "Master NIU ConnID = 7 read permission"; 545 w6 1 rw "Master NIU ConnID = 6 write permission"; 546 r6 1 rw "Master NIU ConnID = 6 read permission"; 547 w5 1 rw "Master NIU ConnID = 5 write permission"; 548 r5 1 rw "Master NIU ConnID = 5 read permission"; 549 w4 1 rw "Master NIU ConnID = 4 write permission"; 550 r4 1 rw "Master NIU ConnID = 4 read permission"; 551 w3 1 rw "Master NIU ConnID = 3 write permission"; 552 r3 1 rw "Master NIU ConnID = 3 read permission"; 553 w2 1 rw "Master NIU ConnID = 2 write permission"; 554 r2 1 rw "Master NIU ConnID = 2 read permission"; 555 w1 1 rw "Master NIU ConnID = 1 write permission"; 556 r1 1 rw "Master NIU ConnID = 1 read permission"; 557 w0 1 rw "Master NIU ConnID = 0 write permission"; 558 r0 1 rw "Master NIU ConnID = 0 read permission"; 559 }; 560 561 register mrm_permission_region_high_j_4 addr(base, 0xCC) "Region j Permission High" { 562 _ 6 rsvd; 563 w12 1 rw "Master NIU ConnID = 12 write permission"; 564 r12 1 rw "Master NIU ConnID = 12 read permission"; 565 _ 1 rsvd; 566 _ 1 rsvd; 567 w10 1 rw "Master NIU ConnID = 10 write permission"; 568 r10 1 rw "Master NIU ConnID = 10 read permission"; 569 w9 1 rw "Master NIU ConnID = 9 write permission"; 570 r9 1 rw "Master NIU ConnID = 9 read permission"; 571 w8 1 rw "Master NIU ConnID = 8 write permission"; 572 r8 1 rw "Master NIU ConnID = 8 read permission"; 573 w7 1 rw "Master NIU ConnID = 7 write permission"; 574 r7 1 rw "Master NIU ConnID = 7 read permission"; 575 w6 1 rw "Master NIU ConnID = 6 write permission"; 576 r6 1 rw "Master NIU ConnID = 6 read permission"; 577 w5 1 rw "Master NIU ConnID = 5 write permission"; 578 r5 1 rw "Master NIU ConnID = 5 read permission"; 579 w4 1 rw "Master NIU ConnID = 4 write permission"; 580 r4 1 rw "Master NIU ConnID = 4 read permission"; 581 w3 1 rw "Master NIU ConnID = 3 write permission"; 582 r3 1 rw "Master NIU ConnID = 3 read permission"; 583 w2 1 rw "Master NIU ConnID = 2 write permission"; 584 r2 1 rw "Master NIU ConnID = 2 read permission"; 585 w1 1 rw "Master NIU ConnID = 1 write permission"; 586 r1 1 rw "Master NIU ConnID = 1 read permission"; 587 w0 1 rw "Master NIU ConnID = 0 write permission"; 588 r0 1 rw "Master NIU ConnID = 0 read permission"; 589 }; 590 591 register mrm_permission_region_high_j_5 addr(base, 0xDC) "Region j Permission High" { 592 _ 6 rsvd; 593 w12 1 rw "Master NIU ConnID = 12 write permission"; 594 r12 1 rw "Master NIU ConnID = 12 read permission"; 595 _ 1 rsvd; 596 _ 1 rsvd; 597 w10 1 rw "Master NIU ConnID = 10 write permission"; 598 r10 1 rw "Master NIU ConnID = 10 read permission"; 599 w9 1 rw "Master NIU ConnID = 9 write permission"; 600 r9 1 rw "Master NIU ConnID = 9 read permission"; 601 w8 1 rw "Master NIU ConnID = 8 write permission"; 602 r8 1 rw "Master NIU ConnID = 8 read permission"; 603 w7 1 rw "Master NIU ConnID = 7 write permission"; 604 r7 1 rw "Master NIU ConnID = 7 read permission"; 605 w6 1 rw "Master NIU ConnID = 6 write permission"; 606 r6 1 rw "Master NIU ConnID = 6 read permission"; 607 w5 1 rw "Master NIU ConnID = 5 write permission"; 608 r5 1 rw "Master NIU ConnID = 5 read permission"; 609 w4 1 rw "Master NIU ConnID = 4 write permission"; 610 r4 1 rw "Master NIU ConnID = 4 read permission"; 611 w3 1 rw "Master NIU ConnID = 3 write permission"; 612 r3 1 rw "Master NIU ConnID = 3 read permission"; 613 w2 1 rw "Master NIU ConnID = 2 write permission"; 614 r2 1 rw "Master NIU ConnID = 2 read permission"; 615 w1 1 rw "Master NIU ConnID = 1 write permission"; 616 r1 1 rw "Master NIU ConnID = 1 read permission"; 617 w0 1 rw "Master NIU ConnID = 0 write permission"; 618 r0 1 rw "Master NIU ConnID = 0 read permission"; 619 }; 620 621 register mrm_permission_region_high_j_6 addr(base, 0xEC) "Region j Permission High" { 622 _ 6 rsvd; 623 w12 1 rw "Master NIU ConnID = 12 write permission"; 624 r12 1 rw "Master NIU ConnID = 12 read permission"; 625 _ 1 rsvd; 626 _ 1 rsvd; 627 w10 1 rw "Master NIU ConnID = 10 write permission"; 628 r10 1 rw "Master NIU ConnID = 10 read permission"; 629 w9 1 rw "Master NIU ConnID = 9 write permission"; 630 r9 1 rw "Master NIU ConnID = 9 read permission"; 631 w8 1 rw "Master NIU ConnID = 8 write permission"; 632 r8 1 rw "Master NIU ConnID = 8 read permission"; 633 w7 1 rw "Master NIU ConnID = 7 write permission"; 634 r7 1 rw "Master NIU ConnID = 7 read permission"; 635 w6 1 rw "Master NIU ConnID = 6 write permission"; 636 r6 1 rw "Master NIU ConnID = 6 read permission"; 637 w5 1 rw "Master NIU ConnID = 5 write permission"; 638 r5 1 rw "Master NIU ConnID = 5 read permission"; 639 w4 1 rw "Master NIU ConnID = 4 write permission"; 640 r4 1 rw "Master NIU ConnID = 4 read permission"; 641 w3 1 rw "Master NIU ConnID = 3 write permission"; 642 r3 1 rw "Master NIU ConnID = 3 read permission"; 643 w2 1 rw "Master NIU ConnID = 2 write permission"; 644 r2 1 rw "Master NIU ConnID = 2 read permission"; 645 w1 1 rw "Master NIU ConnID = 1 write permission"; 646 r1 1 rw "Master NIU ConnID = 1 read permission"; 647 w0 1 rw "Master NIU ConnID = 0 write permission"; 648 r0 1 rw "Master NIU ConnID = 0 read permission"; 649 }; 650 651 register mrm_permission_region_high_j_7 addr(base, 0xFC) "Region j Permission High" { 652 _ 6 rsvd; 653 w12 1 rw "Master NIU ConnID = 12 write permission"; 654 r12 1 rw "Master NIU ConnID = 12 read permission"; 655 _ 1 rsvd; 656 _ 1 rsvd; 657 w10 1 rw "Master NIU ConnID = 10 write permission"; 658 r10 1 rw "Master NIU ConnID = 10 read permission"; 659 w9 1 rw "Master NIU ConnID = 9 write permission"; 660 r9 1 rw "Master NIU ConnID = 9 read permission"; 661 w8 1 rw "Master NIU ConnID = 8 write permission"; 662 r8 1 rw "Master NIU ConnID = 8 read permission"; 663 w7 1 rw "Master NIU ConnID = 7 write permission"; 664 r7 1 rw "Master NIU ConnID = 7 read permission"; 665 w6 1 rw "Master NIU ConnID = 6 write permission"; 666 r6 1 rw "Master NIU ConnID = 6 read permission"; 667 w5 1 rw "Master NIU ConnID = 5 write permission"; 668 r5 1 rw "Master NIU ConnID = 5 read permission"; 669 w4 1 rw "Master NIU ConnID = 4 write permission"; 670 r4 1 rw "Master NIU ConnID = 4 read permission"; 671 w3 1 rw "Master NIU ConnID = 3 write permission"; 672 r3 1 rw "Master NIU ConnID = 3 read permission"; 673 w2 1 rw "Master NIU ConnID = 2 write permission"; 674 r2 1 rw "Master NIU ConnID = 2 read permission"; 675 w1 1 rw "Master NIU ConnID = 1 write permission"; 676 r1 1 rw "Master NIU ConnID = 1 read permission"; 677 w0 1 rw "Master NIU ConnID = 0 write permission"; 678 r0 1 rw "Master NIU ConnID = 0 read permission"; 679 }; 680};