1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_l3init_prm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_l3init_prm msbfirst ( addr base ) "" { 29 30 31 constants l3init_bank1_onstate_status width(2) "" { 32 L3INIT_BANK1_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON."; 33 }; 34 35 constants l3init_bank1_retstate_status width(1) "" { 36 L3INIT_BANK1_RETSTATE_0_r = 0 "Memory bank is off when the domain is in the RETENTION state."; 37 }; 38 39 constants lowpowerstatechange_status width(1) "" { 40 LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change."; 41 LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON."; 42 }; 43 44 constants logicretstate_status width(1) "" { 45 LOGICRETSTATE_0 = 0 "Only retention registers are retained and remaing logic is off when the domain is in RETENTION state."; 46 LOGICRETSTATE_1 = 1 "Whole logic is retained when domain is in RETENTION state."; 47 }; 48 49 constants powerstate_status width(2) "" { 50 POWERSTATE_0 = 0 "OFF state"; 51 POWERSTATE_1 = 1 "RETENTION state"; 52 POWERSTATE_2 = 2 "INACTIVE state"; 53 POWERSTATE_3 = 3 "ON State"; 54 }; 55 56 register pm_l3init_pwrstctrl addr(base, 0x0) "This register controls the L3INIT power state to reach upon a domain sleep transition" { 57 _ 14 mbz; 58 l3init_bank1_onstate 2 ro type(l3init_bank1_onstate_status) "L3INIT BANK state when domain is ON."; 59 _ 7 mbz; 60 l3init_bank1_retstate 1 ro type(l3init_bank1_retstate_status) "L3INIT BANK1 state when domain is RETENTION."; 61 _ 3 mbz; 62 lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."; 63 _ 1 mbz; 64 logicretstate 1 rw type(logicretstate_status) "Logic state when power domain is RETENTION"; 65 powerstate 2 rw type(powerstate_status) "Power state control"; 66 }; 67 68 constants lastpowerstateentered_status width(2) "" { 69 LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE"; 70 LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE"; 71 LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION"; 72 LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF"; 73 }; 74 75 constants intransition_status width(1) "" { 76 INTRANSITION_0_r = 0 "No ongoing transition on power domain"; 77 INTRANSITION_1_r = 1 "Power domain transition is in progress."; 78 }; 79 80 constants l3init_bank1_statest_status width(2) "" { 81 L3INIT_BANK1_STATEST_0_r = 0 "Memory is OFF"; 82 L3INIT_BANK1_STATEST_1_r = 1 "Reserved"; 83 L3INIT_BANK1_STATEST_2_r = 2 "Reserved"; 84 L3INIT_BANK1_STATEST_3_r = 3 "Memory is ON"; 85 }; 86 87 constants logicstatest_status width(1) "" { 88 LOGICSTATEST_0_r = 0 "Logic in domain is OFF"; 89 LOGICSTATEST_1_r = 1 "Logic in domain is ON"; 90 }; 91 92 constants powerstatest_status width(2) "" { 93 POWERSTATEST_0_r = 0 "Power domain is OFF"; 94 POWERSTATEST_1_r = 1 "Power domain is in RETENTION"; 95 POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE"; 96 POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE"; 97 }; 98 99 register pm_l3init_pwrstst addr(base, 0x4) "This register provides a status on the current L3INIT power domain state. [warm reset insensitive]" { 100 _ 6 mbz; 101 lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only."; 102 _ 3 mbz; 103 intransition 1 ro type(intransition_status) "Domain transition status"; 104 _ 14 mbz; 105 l3init_bank1_statest 2 ro type(l3init_bank1_statest_status) "L3INIT BANK1 state status"; 106 _ 1 mbz; 107 logicstatest 1 ro type(logicstatest_status) "Logic state status"; 108 powerstatest 2 ro type(powerstatest_status) "Current power state status"; 109 }; 110 111 constants wkupdep_mmc1_sdma_status width(1) "" { 112 WKUPDEP_MMC1_SDMA_0 = 0 "Dependency is disabled"; 113 WKUPDEP_MMC1_SDMA_1 = 1 "Dependency is enabled"; 114 }; 115 116 register pm_l3init_mmc1_wkdep addr(base, 0x28) "This register controls wakeup dependency based on MMC1 service requests." { 117 _ 28 mbz; 118 wkupdep_mmc1_sdma 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards SDMA + L3_2 + L4PER domains"; 119 wkupdep_mmc1_dsp 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards DSP + L3_1 + L3_2 + L4_PER domains"; 120 wkupdep_mmc1_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards MPU_A3 + L3_2 + L4_PER domains"; 121 wkupdep_mmc1_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC1 module (softwareakeup signal) towards MPU + L3_1 + L3_2 + L4_PER domains"; 122 }; 123 124 constants lostmem_l3init_bank1_status width(1) "" { 125 LOSTMEM_L3INIT_BANK1_0 = 0 "Context has been maintained"; 126 LOSTMEM_L3INIT_BANK1_1 = 1 "Context has been lost"; 127 }; 128 129 register rm_l3init_mmc1_context addr(base, 0x2C) "This register contains dedicated MMC1 context statuses. [warm reset insensitive]" { 130 _ 23 mbz; 131 lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source."; 132 _ 6 mbz; 133 lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)"; 134 _ 1 mbz; 135 }; 136 137 register pm_l3init_mmc2_wkdep addr(base, 0x30) "This register controls wakeup dependency based on MMC2 service requests." { 138 _ 28 mbz; 139 wkupdep_mmc2_sdma 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards SDMA + L3_2 + L4PER domains"; 140 wkupdep_mmc2_dsp 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards DSP + L3_1 + L3_2 + L4_PER domains"; 141 wkupdep_mmc2_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards MPU_A3 + L3_2 + L4_PER domains"; 142 wkupdep_mmc2_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from MMC2 module (softwareakeup signal) towards MPU + L3_1 + L3_2 + L4_PER domains"; 143 }; 144 145 register rm_l3init_mmc2_context addr(base, 0x34) "This register contains dedicated MMC2 context statuses. [warm reset insensitive]" { 146 _ 23 mbz; 147 lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source."; 148 _ 6 mbz; 149 lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)"; 150 _ 1 mbz; 151 }; 152 153 register pm_l3init_hsi_wkdep addr(base, 0x38) "This register controls wakeup dependency based on HSI service requests." { 154 _ 23 mbz; 155 wkupdep_wgm_hsi_wake_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from modem HSI_WAKE signal towards MPU + L3_1 + L4_CFG domains"; 156 _ 1 mbz; 157 wkupdep_hsi_dsp_dsp 1 ro type(wkupdep_mmc1_sdma_status) "Wakeup dependency from HSI module (softwareakeup_DSP signal) towards DSP + L3_1 + L4_CFG domains"; 158 _ 4 mbz; 159 wkupdep_hsi_mcu_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from HSI module (softwareakeup_MPU signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains"; 160 wkupdep_hsi_mcu_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from HSI module (softwareakeup_MPU signal) towards MPU + L3_1 + L4_CFG domains"; 161 }; 162 163 register rm_l3init_hsi_context addr(base, 0x3C) "This register contains dedicated HSI context statuses. [warm reset insensitive]" { 164 _ 23 mbz; 165 lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source."; 166 _ 6 mbz; 167 lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)"; 168 _ 1 mbz; 169 }; 170 171 register pm_l3init_hsusbhost_wkdep addr(base, 0x58) "This register controls wakeup dependency based on USB_HOST_HS service requests." { 172 _ 30 mbz; 173 wkupdep_hsusbhost_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_HS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains"; 174 wkupdep_hsusbhost_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_HS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains"; 175 }; 176 177 register rm_l3init_hsusbhost_context addr(base, 0x5C) "This register contains dedicated USB_HOST context statuses. [warm reset insensitive]" { 178 _ 30 mbz; 179 lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)"; 180 _ 1 mbz; 181 }; 182 183 register pm_l3init_hsusbotg_wkdep addr(base, 0x60) "This register controls wakeup dependency based on USB_OTG_HS service requests." { 184 _ 30 mbz; 185 wkupdep_hsusbotg_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_OTG_HS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains"; 186 wkupdep_hsusbotg_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_OTG_HS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains"; 187 }; 188 189 register rm_l3init_hsusbotg_context addr(base, 0x64) "This register contains dedicated USB_OTG_HS context statuses. [warm reset insensitive]" { 190 _ 23 mbz; 191 lostmem_l3init_bank1 1 rw1c type(lostmem_l3init_bank1_status) "Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source."; 192 _ 6 mbz; 193 lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)"; 194 _ 1 mbz; 195 }; 196 197 register pm_l3init_hsusbtll_wkdep addr(base, 0x68) "This register controls wakeup dependency based on USB_TLL service requests." { 198 _ 30 mbz; 199 wkupdep_hsusbtll_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_TLL module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains"; 200 wkupdep_hsusbtll_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_TLL module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains"; 201 }; 202 203 register rm_l3init_hsusbtll_context addr(base, 0x6C) "This register contains dedicated USB_TLL context statuses. [warm reset insensitive]" { 204 _ 30 mbz; 205 lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)"; 206 _ 1 mbz; 207 }; 208 209 register pm_l3init_fsusb_wkdep addr(base, 0xD0) "This register controls wakeup dependency based on USB_HOST_FS service requests." { 210 _ 30 mbz; 211 wkupdep_fsusb_mpu_m3 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_FS module (softwareakeup signal) towards MPU_A3 + L3_2 + L3_1 + L4_CFG domains"; 212 wkupdep_fsusb_mpu 1 rw type(wkupdep_mmc1_sdma_status) "Wakeup dependency from USB_HOST_FS module (softwareakeup signal) towards MPU + L3_1 + L4_CFG domains"; 213 }; 214 215 register rm_l3init_fsusb_context addr(base, 0xD4) "This register contains dedicated USB_HOST_FS context statuses. [warm reset insensitive]" { 216 _ 30 mbz; 217 lostcontext_rff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RET_RST signal)"; 218 _ 1 mbz; 219 }; 220 221 register rm_l3init_usbphy_context addr(base, 0xE4) "This register contains dedicated USBPHY context statuses. [warm reset insensitive]" { 222 _ 31 mbz; 223 lostcontext_dff 1 rw1c type(lostmem_l3init_bank1_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3_INIT_RST signal)"; 224 }; 225};