1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_iss_top.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_iss_top msbfirst ( addr base ) "" { 29 30 31 register iss_hl_revision ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32); 32 33 constants standbymode_status width(2) "" { 34 STANDBYMODE_0 = 0 "Force-standby. MStandby is asserted unconditionally."; 35 STANDBYMODE_1 = 1 "No-standby. MStandby is never asserted."; 36 STANDBYMODE_3 = 3 "Smart-standby"; 37 STANDBYMODE_2 = 2 "Smart-standby"; 38 }; 39 40 constants idlemode_status width(2) "" { 41 IDLEMODE_0 = 0 "Force-idle"; 42 IDLEMODE_1 = 1 "No-idle"; 43 IDLEMODE_3 = 3 "Smart-idle"; 44 IDLEMODE_2 = 2 "Smart-idle"; 45 }; 46 47 constants softreset_status width(1) "" { 48 SOFTRESET_0_w = 0 "No action"; 49 SOFTRESET_1_w = 1 "Initiate software reset"; 50 SOFTRESET_1_r = 1 "Reset (software or other) ongoing"; 51 SOFTRESET_0_r = 0 "Reset done, no pending action"; 52 }; 53 54 register iss_hl_sysconfig addr(base, 0x10) "Clock management configuration" { 55 _ 26 mbz; 56 standbymode 2 rw type(standbymode_status) "Master interface power management, standby/Wait control"; 57 idlemode 2 rw type(idlemode_status) "IDLE protocol configuration"; 58 _ 1 mbz; 59 softreset 1 rw type(softreset_status) "Software reset."; 60 }; 61 62 constants hs_vs_irq_status width(1) "" { 63 HS_VS_IRQ_0_w = 0 "No action"; 64 HS_VS_IRQ_1_w = 1 "Set event (debug)"; 65 HS_VS_IRQ_1_r = 1 "Event pending"; 66 HS_VS_IRQ_0_r = 0 "No event pending"; 67 }; 68 69 register iss_hl_irqstatus_raw_i_0 addr(base, 0x20) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." { 70 _ 14 mbz; 71 hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 72 ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 73 simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 74 simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 75 simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 76 simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 77 bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine"; 78 cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer"; 79 ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 80 ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 81 ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 82 ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 83 csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b"; 84 csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a"; 85 isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 86 isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 87 isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 88 isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 89 }; 90 91 register iss_hl_irqstatus_raw_i_1 addr(base, 0x30) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." { 92 _ 14 mbz; 93 hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 94 ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 95 simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 96 simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 97 simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 98 simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 99 bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine"; 100 cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer"; 101 ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 102 ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 103 ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 104 ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 105 csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b"; 106 csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a"; 107 isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 108 isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 109 isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 110 isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 111 }; 112 113 register iss_hl_irqstatus_raw_i_2 addr(base, 0x40) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." { 114 _ 14 mbz; 115 hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 116 ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 117 simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 118 simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 119 simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 120 simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 121 bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine"; 122 cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer"; 123 ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 124 ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 125 ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 126 ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 127 csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b"; 128 csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a"; 129 isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 130 isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 131 isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 132 isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 133 }; 134 135 register iss_hl_irqstatus_raw_i_3 addr(base, 0x50) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." { 136 _ 14 mbz; 137 hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 138 ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 139 simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 140 simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 141 simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 142 simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 143 bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine"; 144 cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer"; 145 ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 146 ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 147 ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 148 ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 149 csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b"; 150 csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a"; 151 isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 152 isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 153 isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 154 isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 155 }; 156 157 register iss_hl_irqstatus_raw_i_4 addr(base, 0x60) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." { 158 _ 14 mbz; 159 hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 160 ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 161 simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 162 simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 163 simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 164 simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 165 bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine"; 166 cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer"; 167 ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 168 ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 169 ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 170 ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 171 csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b"; 172 csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a"; 173 isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 174 isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 175 isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 176 isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 177 }; 178 179 register iss_hl_irqstatus_raw_i_5 addr(base, 0x70) "Per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled by setting the register." { 180 _ 14 mbz; 181 hs_vs_irq 1 rw type(hs_vs_irq_status) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 182 ccp2_irq8 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 183 simcop_irq3 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 184 simcop_irq2 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 185 simcop_irq1 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 186 simcop_irq0 1 ro type(hs_vs_irq_status) "Event generated by SIMCOP"; 187 bte_irq 1 ro type(hs_vs_irq_status) "Event generated by the burst translation engine"; 188 cbuff_irq 1 ro type(hs_vs_irq_status) "Event generated by the circular buffer"; 189 ccp2_irq3 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 190 ccp2_irq2 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 191 ccp2_irq1 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 192 ccp2_irq0 1 ro type(hs_vs_irq_status) "Event generated by the CCP2 receiver"; 193 csib_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #b"; 194 csia_irq 1 ro type(hs_vs_irq_status) "Event generated by the CSI2 receiver #a"; 195 isp_irq3 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 196 isp_irq2 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 197 isp_irq1 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 198 isp_irq0 1 ro type(hs_vs_irq_status) "Combined interrupt event provided by the ISP."; 199 }; 200 201 constants hs_vs_irq_status1 width(1) "" { 202 HS_VS_IRQ_0_w_6 = 0 "No action"; 203 HS_VS_IRQ_1_w_6 = 1 "Clear (raw) event"; 204 HS_VS_IRQ_1_r_6 = 1 "Event pending"; 205 HS_VS_IRQ_0_r_6 = 0 "No (enabled) event pending"; 206 }; 207 208 register iss_hl_irqstatus_i_0 addr(base, 0x24) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." { 209 _ 14 mbz; 210 hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 211 ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 212 simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 213 simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 214 simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 215 simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 216 bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine"; 217 cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer"; 218 ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 219 ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 220 ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 221 ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 222 csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b"; 223 csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a"; 224 isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 225 isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 226 isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 227 isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 228 }; 229 230 register iss_hl_irqstatus_i_1 addr(base, 0x34) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." { 231 _ 14 mbz; 232 hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 233 ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 234 simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 235 simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 236 simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 237 simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 238 bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine"; 239 cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer"; 240 ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 241 ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 242 ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 243 ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 244 csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b"; 245 csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a"; 246 isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 247 isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 248 isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 249 isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 250 }; 251 252 register iss_hl_irqstatus_i_2 addr(base, 0x44) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." { 253 _ 14 mbz; 254 hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 255 ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 256 simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 257 simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 258 simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 259 simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 260 bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine"; 261 cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer"; 262 ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 263 ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 264 ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 265 ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 266 csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b"; 267 csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a"; 268 isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 269 isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 270 isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 271 isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 272 }; 273 274 register iss_hl_irqstatus_i_3 addr(base, 0x54) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." { 275 _ 14 mbz; 276 hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 277 ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 278 simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 279 simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 280 simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 281 simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 282 bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine"; 283 cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer"; 284 ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 285 ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 286 ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 287 ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 288 csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b"; 289 csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a"; 290 isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 291 isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 292 isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 293 isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 294 }; 295 296 register iss_hl_irqstatus_i_4 addr(base, 0x64) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." { 297 _ 14 mbz; 298 hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 299 ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 300 simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 301 simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 302 simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 303 simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 304 bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine"; 305 cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer"; 306 ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 307 ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 308 ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 309 ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 310 csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b"; 311 csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a"; 312 isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 313 isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 314 isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 315 isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 316 }; 317 318 register iss_hl_irqstatus_i_5 addr(base, 0x74) "Per-event 'enabled' interrupt status vector, line 0. Enabled status is not set unless event is enabled by setting the register." { 319 _ 14 mbz; 320 hs_vs_irq 1 rw type(hs_vs_irq_status1) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 321 ccp2_irq8 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 322 simcop_irq3 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 323 simcop_irq2 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 324 simcop_irq1 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 325 simcop_irq0 1 ro type(hs_vs_irq_status1) "Event generated by SIMCOP"; 326 bte_irq 1 ro type(hs_vs_irq_status1) "Event generated by the burst translation engine"; 327 cbuff_irq 1 ro type(hs_vs_irq_status1) "Event generated by the circular buffer"; 328 ccp2_irq3 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 329 ccp2_irq2 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 330 ccp2_irq1 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 331 ccp2_irq0 1 ro type(hs_vs_irq_status1) "Event generated by the CCP2 receiver"; 332 csib_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #b"; 333 csia_irq 1 ro type(hs_vs_irq_status1) "Event generated by the CSI2 receiver #a"; 334 isp_irq3 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 335 isp_irq2 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 336 isp_irq1 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 337 isp_irq0 1 ro type(hs_vs_irq_status1) "Combined interrupt event provided by the ISP."; 338 }; 339 340 constants hs_vs_irq_status2 width(1) "" { 341 HS_VS_IRQ_0_w_12 = 0 "No action"; 342 HS_VS_IRQ_1_w_12 = 1 "Enable interrupt"; 343 HS_VS_IRQ_1_r_12 = 1 "Interrupt enabled"; 344 HS_VS_IRQ_0_r_12 = 0 "Interrupt disabled (masked)"; 345 }; 346 347 constants ccp2_irq8_status width(1) "" { 348 CCP2_IRQ8_0_w = 0 "No action Write 0x1: Enable interrupt"; 349 CCP2_IRQ8_1_r_12 = 1 "Interrupt enabled Read 0x0: Interrupt disabled (masked)"; 350 }; 351 352 register iss_hl_irqenable_set_i_0 addr(base, 0x28) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 353 _ 14 mbz; 354 hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 355 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 356 simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 357 simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 358 simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 359 simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 360 bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine"; 361 cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer"; 362 ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 363 ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 364 ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 365 ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 366 csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b"; 367 csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a"; 368 isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 369 isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 370 isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 371 isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 372 }; 373 374 register iss_hl_irqenable_set_i_1 addr(base, 0x38) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 375 _ 14 mbz; 376 hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 377 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 378 simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 379 simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 380 simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 381 simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 382 bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine"; 383 cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer"; 384 ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 385 ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 386 ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 387 ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 388 csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b"; 389 csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a"; 390 isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 391 isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 392 isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 393 isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 394 }; 395 396 register iss_hl_irqenable_set_i_2 addr(base, 0x48) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 397 _ 14 mbz; 398 hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 399 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 400 simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 401 simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 402 simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 403 simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 404 bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine"; 405 cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer"; 406 ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 407 ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 408 ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 409 ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 410 csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b"; 411 csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a"; 412 isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 413 isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 414 isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 415 isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 416 }; 417 418 register iss_hl_irqenable_set_i_3 addr(base, 0x58) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 419 _ 14 mbz; 420 hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 421 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 422 simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 423 simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 424 simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 425 simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 426 bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine"; 427 cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer"; 428 ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 429 ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 430 ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 431 ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 432 csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b"; 433 csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a"; 434 isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 435 isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 436 isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 437 isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 438 }; 439 440 register iss_hl_irqenable_set_i_4 addr(base, 0x68) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 441 _ 14 mbz; 442 hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 443 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 444 simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 445 simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 446 simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 447 simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 448 bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine"; 449 cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer"; 450 ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 451 ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 452 ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 453 ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 454 csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b"; 455 csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a"; 456 isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 457 isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 458 isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 459 isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 460 }; 461 462 register iss_hl_irqenable_set_i_5 addr(base, 0x78) "Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 463 _ 14 mbz; 464 hs_vs_irq 1 rw type(hs_vs_irq_status2) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 465 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 466 simcop_irq3 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 467 simcop_irq2 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 468 simcop_irq1 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 469 simcop_irq0 1 rw type(hs_vs_irq_status2) "Event generated by SIMCOP"; 470 bte_irq 1 rw type(hs_vs_irq_status2) "Event generated by the burst translation engine"; 471 cbuff_irq 1 rw type(hs_vs_irq_status2) "Event generated by the circular buffer"; 472 ccp2_irq3 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 473 ccp2_irq2 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 474 ccp2_irq1 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 475 ccp2_irq0 1 rw type(hs_vs_irq_status2) "Event generated by the CCP2 receiver"; 476 csib_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #b"; 477 csia_irq 1 rw type(hs_vs_irq_status2) "Event generated by the CSI2 receiver #a"; 478 isp_irq3 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 479 isp_irq2 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 480 isp_irq1 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 481 isp_irq0 1 rw type(hs_vs_irq_status2) "Combined interrupt event provided by the ISP."; 482 }; 483 484 constants hs_vs_irq_status3 width(1) "" { 485 HS_VS_IRQ_0_w_18 = 0 "No action"; 486 HS_VS_IRQ_1_w_18 = 1 "Disable interrupt"; 487 HS_VS_IRQ_1_r_18 = 1 "Interrupt enabled"; 488 HS_VS_IRQ_0_r_18 = 0 "Interrupt disabled (masked)"; 489 }; 490 491 register iss_hl_irqenable_clr_i_0 addr(base, 0x2C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 492 _ 14 mbz; 493 hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 494 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 495 simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 496 simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 497 simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 498 simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 499 bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE"; 500 cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF"; 501 ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 502 ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 503 ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 504 ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 505 csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b"; 506 csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a"; 507 isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 508 isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 509 isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 510 isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 511 }; 512 513 register iss_hl_irqenable_clr_i_1 addr(base, 0x3C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 514 _ 14 mbz; 515 hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 516 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 517 simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 518 simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 519 simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 520 simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 521 bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE"; 522 cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF"; 523 ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 524 ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 525 ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 526 ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 527 csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b"; 528 csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a"; 529 isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 530 isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 531 isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 532 isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 533 }; 534 535 register iss_hl_irqenable_clr_i_2 addr(base, 0x4C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 536 _ 14 mbz; 537 hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 538 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 539 simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 540 simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 541 simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 542 simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 543 bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE"; 544 cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF"; 545 ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 546 ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 547 ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 548 ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 549 csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b"; 550 csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a"; 551 isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 552 isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 553 isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 554 isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 555 }; 556 557 register iss_hl_irqenable_clr_i_3 addr(base, 0x5C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 558 _ 14 mbz; 559 hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 560 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 561 simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 562 simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 563 simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 564 simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 565 bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE"; 566 cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF"; 567 ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 568 ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 569 ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 570 ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 571 csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b"; 572 csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a"; 573 isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 574 isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 575 isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 576 isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 577 }; 578 579 register iss_hl_irqenable_clr_i_4 addr(base, 0x6C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 580 _ 14 mbz; 581 hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 582 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 583 simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 584 simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 585 simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 586 simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 587 bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE"; 588 cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF"; 589 ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 590 ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 591 ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 592 ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 593 csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b"; 594 csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a"; 595 isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 596 isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 597 isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 598 isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 599 }; 600 601 register iss_hl_irqenable_clr_i_5 addr(base, 0x7C) "Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 602 _ 14 mbz; 603 hs_vs_irq 1 rw1c type(hs_vs_irq_status3) "HS or VS synchronization event. This event is triggered if a rising or falling edge is detected on the HS or VS signal (after the video port mux). The rising or falling edge and the HS or VS signal selection is chosen with the ISS_CTRL.SYNC_DETECT bit field."; 604 ccp2_irq8 1 rw type(ccp2_irq8_status) "Event generated by the CCP2 receiver"; 605 simcop_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 606 simcop_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 607 simcop_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 608 simcop_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by SIMCOP"; 609 bte_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the BTE"; 610 cbuff_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CBUFF"; 611 ccp2_irq3 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 612 ccp2_irq2 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 613 ccp2_irq1 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 614 ccp2_irq0 1 rw1c type(hs_vs_irq_status3) "Event generated by the CCP2 receiver"; 615 csib_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver b"; 616 csia_irq 1 rw1c type(hs_vs_irq_status3) "Event generated by the CSI2 receiver a"; 617 isp_irq3 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 618 isp_irq2 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 619 isp_irq1 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 620 isp_irq0 1 rw1c type(hs_vs_irq_status3) "Combined interrupt event provided by the ISP."; 621 }; 622 623 constants iss_clk_div_status width(2) "" { 624 ISS_CLK_DIV_0 = 0 "FCLK=CLK CFGCLK=CLK/2"; 625 ISS_CLK_DIV_1 = 1 "FCLK=CLK/2 CFGCLK=CLK/4"; 626 ISS_CLK_DIV_3 = 3 "Reserved"; 627 ISS_CLK_DIV_2 = 2 "FCLK=CLK/4 CFGCLK=CLK/8"; 628 }; 629 630 constants input_sel_status width(2) "" { 631 INPUT_SEL_0 = 0 "CSI2-A"; 632 INPUT_SEL_1 = 1 "CSI2-B"; 633 INPUT_SEL_2 = 2 "CCP2"; 634 INPUT_SEL_3 = 3 "Parallel interface"; 635 }; 636 637 constants sync_detect_status width(2) "" { 638 SYNC_DETECT_0 = 0 "HS falling edge"; 639 SYNC_DETECT_1 = 1 "HS raising edge"; 640 SYNC_DETECT_3 = 3 "VS raising edge"; 641 SYNC_DETECT_2 = 2 "VS falling edge"; 642 }; 643 644 register iss_ctrl addr(base, 0x80) "ISS control register" { 645 csi2_b_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CSI2 b write bridge. Note: Tag count must be set to 16 for best performance."; 646 csi2_a_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CSI2 a write bridge. Note: Tag count must be set to 16 for best performance."; 647 ccp2w_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CCP2 write bridge Note: Tag count must be set to 16 for best performance."; 648 ccp2r_tag_cnt 4 rw "Defines the maximum number of tags that could be used by the CCP2 read bridge Note: Tag count must be set to 16 for best performance."; 649 _ 10 mbz; 650 iss_clk_div 2 rw type(iss_clk_div_status) "ISS functional clock division CLK refers to the input clock provided to the ISS. FCLK is the functional clock provided to ISS top level and submodules. CFGCLK is the clock used for the configuration network."; 651 input_sel 2 rw type(input_sel_status) "Selects ISP input"; 652 sync_detect 2 rw type(sync_detect_status) "Chooses among rising and falling edge for the HS_VS_IRQ synchronization event"; 653 }; 654 655 constants vport3_clk_status width(1) "" { 656 VPORT3_CLK_0 = 0 "Disabled"; 657 VPORT3_CLK_1 = 1 "Enabled"; 658 }; 659 660 constants ccp2_status width(1) "" { 661 CCP2_0_w = 0 "Request shutdown of the submodule. No effect if the submodule clock is already off."; 662 CCP2_1_w = 1 "Request enable of the submodule. No effect if the submodule clock is already on."; 663 }; 664 665 register iss_clkctrl addr(base, 0x84) "ISS clock control register. Use to enable/disable the interface and functional clock of ISS submodules." { 666 vport3_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the parallel interface"; 667 vport2_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the CCP2 protocol engine"; 668 vport1_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the CSI2_B protocol engine"; 669 vport0_clk 1 rw type(vport3_clk_status) "Enables the pixel clock from the CSI2_A protocol engine"; 670 _ 23 mbz; 671 ccp2 1 wo type(ccp2_status) "CCP2"; 672 csi2_b 1 wo type(ccp2_status) "CSI2_B"; 673 csi2_a 1 wo type(ccp2_status) "CSI2_A"; 674 isp 1 wo type(ccp2_status) "ISP"; 675 simcop 1 wo type(ccp2_status) "SIMCOP"; 676 }; 677 678 constants ccp2_status1 width(1) "" { 679 CCP2_1_r = 1 "The submodule is on."; 680 CCP2_0_r = 0 "The submodule is off."; 681 }; 682 683 register iss_clkstat addr(base, 0x88) "ISS clock status register." { 684 vport3_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the parallel interface"; 685 vport2_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the CCP2 protocol engine"; 686 vport1_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the CSI2_B protocol engine"; 687 vport0_clk 1 ro type(vport3_clk_status) "Status of the pixel clock from the CSI2_A protocol engine"; 688 _ 23 mbz; 689 ccp2 1 ro type(ccp2_status1) "CCP2"; 690 csi2_b 1 ro type(ccp2_status1) "CSI2_B"; 691 csi2_a 1 ro type(ccp2_status1) "CSI2_A"; 692 isp 1 ro type(ccp2_status1) "ISP"; 693 simcop 1 ro type(ccp2_status1) "SIMCOP"; 694 }; 695 696 constants cbuff_pm_status width(2) "" { 697 CBUFF_PM_2_r = 2 "Functional"; 698 CBUFF_PM_1_r = 1 "Transition"; 699 CBUFF_PM_0_r = 0 "Idle"; 700 }; 701 702 constants simcop_pm_status width(2) "" { 703 SIMCOP_PM_2_r = 2 "Functional"; 704 SIMCOP_PM_1_r = 1 "Transition"; 705 SIMCOP_PM_0_r = 0 "Standby"; 706 }; 707 708 register iss_pm_status addr(base, 0x8C) "ISS power manager status register. Software could know what modules are in functional or STANDBY/IDLE state. This feature could be particularly useful to debug when ISS does not go into STANDBY mode" { 709 _ 18 mbz; 710 cbuff_pm 2 ro type(cbuff_pm_status) "Power status of the CBUFF."; 711 bte_pm 2 ro type(cbuff_pm_status) "Power status of the BTE."; 712 simcop_pm 2 ro type(simcop_pm_status) "Power status of the SIMCOP."; 713 isp_pm 2 ro type(simcop_pm_status) "Power status of the ISP."; 714 ccp2_pm 2 ro type(simcop_pm_status) "Power status of the CCP2."; 715 csi2_b_pm 2 ro type(simcop_pm_status) "Power status of the CSI2 module b"; 716 csi2_a_pm 2 ro type(simcop_pm_status) "Power status of the CSI2 module a"; 717 }; 718};