1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_iss_isp5_sys2.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_iss_isp5_sys2 msbfirst ( addr base ) "" { 29 30 31 constants key1_en_status width(1) "" { 32 KEY1_EN_1_r = 1 "Enable"; 33 KEY1_EN_0_r = 0 "Disable"; 34 }; 35 36 register isp5_key_en1 addr(base, 0x0) "IPIPE eFuse enable." { 37 _ 31 mbz; 38 key1_en 1 ro type(key1_en_status) "eFuse enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise."; 39 }; 40 41 register isp5_key_en2 addr(base, 0x4) "ISIF eFuse enable." { 42 _ 31 mbz; 43 key1_en 1 ro type(key1_en_status) "eFuse enable Equals 1 when ISP5_EFUSE1_EN = 1 or 0 otherwise."; 44 }; 45 46 register isp5_key_en3 addr(base, 0x8) "ISIF eFuse enable." { 47 _ 31 mbz; 48 key_en 1 ro type(key1_en_status) "eFuse enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise."; 49 }; 50 51 register isp5_key_en4 addr(base, 0xC) "IPIPEIF eFuse enable." { 52 _ 30 mbz; 53 key2_en 1 ro type(key1_en_status) "eFuse enable Equals 1 when ISP5_EFUSE4_EN = 1 or 0 otherwise."; 54 key1_en 1 ro type(key1_en_status) "eFuse enable Equals 1 when ISP5_EFUSE1_EN = 1 or 0 otherwise."; 55 }; 56 57 register isp5_key_en5 addr(base, 0x10) "H3A eFuse enable." { 58 _ 31 mbz; 59 key_en 1 ro type(key1_en_status) "eFuse enable Equals 1 when ISP5_EFUSE2_EN = 1 or 0 otherwise."; 60 }; 61 62 register isp5_key_en6 addr(base, 0x14) "H3A eFuse enable." { 63 _ 31 mbz; 64 key_en 1 ro type(key1_en_status) "eFuse enable Equals 1 when ISP5_EFUSE3_EN = 1 or 0 otherwise."; 65 }; 66 67 constants ipipe_hst_err_status width(1) "" { 68 IPIPE_HST_ERR_0_w = 0 "No action"; 69 IPIPE_HST_ERR_1_w = 1 "Set event (debug)"; 70 IPIPE_HST_ERR_1_r = 1 "Event pending"; 71 IPIPE_HST_ERR_0_r = 0 "No event pending"; 72 }; 73 74 register isp5_irqstatus_raw2_i_0 addr(base, 0x18) "Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 75 _ 26 mbz; 76 _ 1 mbz; 77 ipipe_hst_err 1 rw type(ipipe_hst_err_status) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit immediately after reading the last data, else this event will be set."; 78 isif_ovf 1 rw type(ipipe_hst_err_status) "ISIF module overflow"; 79 ipipe_boxcar_ovf 1 rw type(ipipe_hst_err_status) "IPIPE BOXCAR module overflow"; 80 ipipeif_udf 1 rw type(ipipe_hst_err_status) "IPIPEIF module underflow interrupt"; 81 h3a_ovf 1 rw type(ipipe_hst_err_status) "H3A module overflow interrupt."; 82 }; 83 84 register isp5_irqstatus_raw2_i_1 addr(base, 0x28) "Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 85 _ 26 mbz; 86 _ 1 mbz; 87 ipipe_hst_err 1 rw type(ipipe_hst_err_status) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit immediately after reading the last data, else this event will be set."; 88 isif_ovf 1 rw type(ipipe_hst_err_status) "ISIF module overflow"; 89 ipipe_boxcar_ovf 1 rw type(ipipe_hst_err_status) "IPIPE BOXCAR module overflow"; 90 ipipeif_udf 1 rw type(ipipe_hst_err_status) "IPIPEIF module underflow interrupt"; 91 h3a_ovf 1 rw type(ipipe_hst_err_status) "H3A module overflow interrupt."; 92 }; 93 94 register isp5_irqstatus_raw2_i_2 addr(base, 0x38) "Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 95 _ 26 mbz; 96 _ 1 mbz; 97 ipipe_hst_err 1 rw type(ipipe_hst_err_status) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit immediately after reading the last data, else this event will be set."; 98 isif_ovf 1 rw type(ipipe_hst_err_status) "ISIF module overflow"; 99 ipipe_boxcar_ovf 1 rw type(ipipe_hst_err_status) "IPIPE BOXCAR module overflow"; 100 ipipeif_udf 1 rw type(ipipe_hst_err_status) "IPIPEIF module underflow interrupt"; 101 h3a_ovf 1 rw type(ipipe_hst_err_status) "H3A module overflow interrupt."; 102 }; 103 104 register isp5_irqstatus_raw2_i_3 addr(base, 0x48) "Per-event raw interrupt status vector. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 105 _ 26 mbz; 106 _ 1 mbz; 107 ipipe_hst_err 1 rw type(ipipe_hst_err_status) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by the MPU or the DMA. When the data is read with the MPU, one need to pay attention to clear the ISP5_CTRL[26] HST_RD_CHK bit immediately after reading the last data, else this event will be set."; 108 isif_ovf 1 rw type(ipipe_hst_err_status) "ISIF module overflow"; 109 ipipe_boxcar_ovf 1 rw type(ipipe_hst_err_status) "IPIPE BOXCAR module overflow"; 110 ipipeif_udf 1 rw type(ipipe_hst_err_status) "IPIPEIF module underflow interrupt"; 111 h3a_ovf 1 rw type(ipipe_hst_err_status) "H3A module overflow interrupt."; 112 }; 113 114 constants ipipe_hst_err_status1 width(1) "" { 115 IPIPE_HST_ERR_0_w_4 = 0 "No action"; 116 IPIPE_HST_ERR_1_w_4 = 1 "Clear (raw) event"; 117 IPIPE_HST_ERR_1_r_4 = 1 "Event pending"; 118 IPIPE_HST_ERR_0_r_4 = 0 "No (enabled) event pending"; 119 }; 120 121 register isp5_irqstatus2_i_0 addr(base, 0x1C) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 122 _ 26 mbz; 123 _ 1 mbz; 124 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status1) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 125 isif_ovf 1 rw1c type(ipipe_hst_err_status1) "ISIF module overflow"; 126 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status1) "IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 127 ipipeif_udf 1 rw1c type(ipipe_hst_err_status1) "IPIPEIF module underflow interrupt"; 128 h3a_ovf 1 rw1c type(ipipe_hst_err_status1) "H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 129 }; 130 131 register isp5_irqstatus2_i_1 addr(base, 0x2C) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 132 _ 26 mbz; 133 _ 1 mbz; 134 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status1) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 135 isif_ovf 1 rw1c type(ipipe_hst_err_status1) "ISIF module overflow"; 136 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status1) "IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 137 ipipeif_udf 1 rw1c type(ipipe_hst_err_status1) "IPIPEIF module underflow interrupt"; 138 h3a_ovf 1 rw1c type(ipipe_hst_err_status1) "H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 139 }; 140 141 register isp5_irqstatus2_i_2 addr(base, 0x3C) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 142 _ 26 mbz; 143 _ 1 mbz; 144 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status1) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 145 isif_ovf 1 rw1c type(ipipe_hst_err_status1) "ISIF module overflow"; 146 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status1) "IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 147 ipipeif_udf 1 rw1c type(ipipe_hst_err_status1) "IPIPEIF module underflow interrupt"; 148 h3a_ovf 1 rw1c type(ipipe_hst_err_status1) "H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 149 }; 150 151 register isp5_irqstatus2_i_3 addr(base, 0x4C) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 152 _ 26 mbz; 153 _ 1 mbz; 154 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status1) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 155 isif_ovf 1 rw1c type(ipipe_hst_err_status1) "ISIF module overflow"; 156 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status1) "IPIPE BOXCAR module overflow Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 157 ipipeif_udf 1 rw1c type(ipipe_hst_err_status1) "IPIPEIF module underflow interrupt"; 158 h3a_ovf 1 rw1c type(ipipe_hst_err_status1) "H3A module overflow interrupt. Overflow errors are not recoverable at ISP level, a software reset is required at ISS level."; 159 }; 160 161 constants h3a_ovf_status width(1) "" { 162 H3A_OVF_0_w_8 = 0 "No action"; 163 H3A_OVF_1_w_8 = 1 "Enable interrupt"; 164 H3A_OVF_1_r_8 = 1 "Interrupt enabled"; 165 H3A_OVF_0_r_8 = 0 "Interrupt disabled"; 166 }; 167 168 register isp5_irqenable_set2_i_0 addr(base, 0x20) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 169 _ 26 mbz; 170 _ 1 mbz; 171 ipipe_hst_err 1 rw "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 172 isif_ovf 1 rw "ISIF module overflow"; 173 ipipe_boxcar_ovf 1 rw "IPIPE BOXCAR module overflow"; 174 ipipeif_udf 1 rw "IPIPEIF module underflow interrupt"; 175 h3a_ovf 1 rw type(h3a_ovf_status) "H3A module overflow interrupt."; 176 }; 177 178 register isp5_irqenable_set2_i_1 addr(base, 0x30) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 179 _ 26 mbz; 180 _ 1 mbz; 181 ipipe_hst_err 1 rw "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 182 isif_ovf 1 rw "ISIF module overflow"; 183 ipipe_boxcar_ovf 1 rw "IPIPE BOXCAR module overflow"; 184 ipipeif_udf 1 rw "IPIPEIF module underflow interrupt"; 185 h3a_ovf 1 rw type(h3a_ovf_status) "H3A module overflow interrupt."; 186 }; 187 188 register isp5_irqenable_set2_i_2 addr(base, 0x40) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 189 _ 26 mbz; 190 _ 1 mbz; 191 ipipe_hst_err 1 rw "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 192 isif_ovf 1 rw "ISIF module overflow"; 193 ipipe_boxcar_ovf 1 rw "IPIPE BOXCAR module overflow"; 194 ipipeif_udf 1 rw "IPIPEIF module underflow interrupt"; 195 h3a_ovf 1 rw type(h3a_ovf_status) "H3A module overflow interrupt."; 196 }; 197 198 register isp5_irqenable_set2_i_3 addr(base, 0x50) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 199 _ 26 mbz; 200 _ 1 mbz; 201 ipipe_hst_err 1 rw "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 202 isif_ovf 1 rw "ISIF module overflow"; 203 ipipe_boxcar_ovf 1 rw "IPIPE BOXCAR module overflow"; 204 ipipeif_udf 1 rw "IPIPEIF module underflow interrupt"; 205 h3a_ovf 1 rw type(h3a_ovf_status) "H3A module overflow interrupt."; 206 }; 207 208 constants ipipe_hst_err_status2 width(1) "" { 209 IPIPE_HST_ERR_0_w_8 = 0 "No action"; 210 IPIPE_HST_ERR_1_w_8 = 1 "Disable Interrupt"; 211 IPIPE_HST_ERR_1_r_8 = 1 "Interrupt enabled"; 212 IPIPE_HST_ERR_0_r_8 = 0 "Interrupt disabled"; 213 }; 214 215 register isp5_irqenable_clr2_i_0 addr(base, 0x24) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 216 _ 26 mbz; 217 _ 1 mbz; 218 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status2) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 219 isif_ovf 1 rw1c type(ipipe_hst_err_status2) "ISIF module overflow"; 220 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status2) "IPIPE BOXCAR module overflow"; 221 ipipeif_udf 1 rw1c type(ipipe_hst_err_status2) "IPIPEIF module underflow interrupt"; 222 h3a_ovf 1 rw1c type(ipipe_hst_err_status2) "H3A module overflow interrupt."; 223 }; 224 225 register isp5_irqenable_clr2_i_1 addr(base, 0x34) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 226 _ 26 mbz; 227 _ 1 mbz; 228 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status2) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 229 isif_ovf 1 rw1c type(ipipe_hst_err_status2) "ISIF module overflow"; 230 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status2) "IPIPE BOXCAR module overflow"; 231 ipipeif_udf 1 rw1c type(ipipe_hst_err_status2) "IPIPEIF module underflow interrupt"; 232 h3a_ovf 1 rw1c type(ipipe_hst_err_status2) "H3A module overflow interrupt."; 233 }; 234 235 register isp5_irqenable_clr2_i_2 addr(base, 0x44) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 236 _ 26 mbz; 237 _ 1 mbz; 238 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status2) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 239 isif_ovf 1 rw1c type(ipipe_hst_err_status2) "ISIF module overflow"; 240 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status2) "IPIPE BOXCAR module overflow"; 241 ipipeif_udf 1 rw1c type(ipipe_hst_err_status2) "IPIPEIF module underflow interrupt"; 242 h3a_ovf 1 rw1c type(ipipe_hst_err_status2) "H3A module overflow interrupt."; 243 }; 244 245 register isp5_irqenable_clr2_i_3 addr(base, 0x54) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. Overflow / underflow errors are not recoverable at ISP level, a software reset is required at ISS level. The ISP outputs 4 interrupt lines ISP5_IRQ0 to ISP5_IRQ3. Any internal ISP event can be merged on the 4 lines. A same event must be enabled on only one interrupt line." { 246 _ 26 mbz; 247 _ 1 mbz; 248 ipipe_hst_err 1 rw1c type(ipipe_hst_err_status2) "IPIPE HISTOGRAM memory read error This error will happen when the histogram data is not read fast enough by either the MPU or the DMA."; 249 isif_ovf 1 rw1c type(ipipe_hst_err_status2) "ISIF module overflow"; 250 ipipe_boxcar_ovf 1 rw1c type(ipipe_hst_err_status2) "IPIPE BOXCAR module overflow"; 251 ipipeif_udf 1 rw1c type(ipipe_hst_err_status2) "IPIPEIF module underflow interrupt"; 252 h3a_ovf 1 rw1c type(ipipe_hst_err_status2) "H3A module overflow interrupt."; 253 }; 254};