1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_hwseq_l3interconnect.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_hwseq_l3interconnect msbfirst ( addr base ) "" { 29 30 31 constants cpu_proc_done_status width(1) "" { 32 CPU_PROC_DONE_0_w = 0 "No effect."; 33 CPU_PROC_DONE_1_w = 1 "CPU processing completed."; 34 }; 35 36 constants bitstream_status width(3) "" { 37 BITSTREAM_0 = 0 "Bank 0: coprocessor bus (0x1000-0x17FF) Bank 1: coprocessor bus (0x1800-0x1FFF)"; 38 BITSTREAM_1 = 1 "Bank 0: DMA (0x1000-0x17FF) Bank 1: DMA (0x1800-0x1FFF)"; 39 BITSTREAM_2 = 2 "Bank 0: VLCDJ.B (0x000-0x7FF) Bank 1: VLCDJ.B (0x800-0xFFF)"; 40 BITSTREAM_3 = 3 "Bank 0: DMA (0x1000-0x17FF) Bank 1: VLCDJ.B (0x800-0xFFF)"; 41 BITSTREAM_4 = 4 "Bank 0: VLCDJ.B (0x000-0x7FF) Bank 1: DMA (0x1800-0x1FFF)"; 42 BITSTREAM_5 = 5 "The bitstream buffer is managed by hardware as a PING/PONG buffer to support JPEG encode use case. It can be accessed by the SIMCOP DMA or the VLCDJ module. The BITSTREAM hardware sequence is reset when the mode is changed to COPR, VLCDJ or DMA."; 43 BITSTREAM_6 = 6 "The bitstream buffer is managed by hardware as a PING/PONG buffer to support JPEG decode use case. It can be accessed by the SIMCOP DMA or the VLCDJ module. The BITSTREAM hardware sequence is reset when the mode is changed to COPR, VLCDJ or DMA."; 44 }; 45 46 constants bitstr_xfer_size_status width(2) "" { 47 BITSTR_XFER_SIZE_0 = 0 "2048 bytes"; 48 BITSTR_XFER_SIZE_1 = 1 "1024 bytes"; 49 BITSTR_XFER_SIZE_2 = 2 "512 bytes"; 50 BITSTR_XFER_SIZE_3 = 3 "256 bytes"; 51 }; 52 53 constants hw_seq_stop_status width(1) "" { 54 HW_SEQ_STOP_0_w = 0 "No effect."; 55 HW_SEQ_STOP_1_w = 1 "Stop the hardware sequence immediately (don't wait for expected DONE events). Setting this bit while the sequencer is idle has no effect."; 56 }; 57 58 constants hw_seq_start_status width(1) "" { 59 HW_SEQ_START_0_w = 0 "No effect."; 60 HW_SEQ_START_1_w = 1 "Starts step number[12:11] STEP of the hardware sequence. Setting this bit while the sequencer is running has no effect."; 61 }; 62 63 register simcop_hwseq_ctrl addr(base, 0x68) "SIMCOP hardware sequencer control register" { 64 hw_seq_step_counter 16 rw "Number of steps executed by the hardware sequencer. HW_SEQ_STEP_COUNTER=0 corresponds to manual sequencing."; 65 _ 3 mbz; 66 step 2 rw "This register is automatically updated by the hardware sequencer when it is active. Otherwise, software can use it to activate the content of a given set of step registers (SIMCOP_HWSEQ_STEP_i) or to choose the first step number of a sequence."; 67 cpu_proc_done 1 wo type(cpu_proc_done_status) "Used by the CPU to tell that it has completed data processing. This feature should be used together with the CPU_PROC_START_IRQ event Read's always return 0."; 68 bbm_sync_chan 2 rw "Defines the SIMCOP DMA hardware synchronization channel to be used for BBM. This register is only used when BITSTREAM=ENCODE or DECODE. Software must ensure that the same DMA hardware synchronization channel is not used by the hardware sequencer."; 69 bbm_status 1 ro "Status of the Bitstream buffer management hardware.Used only during automatic mode [BITSTREAM=5 or 6]. Equals 0 (IDLE) in manual mode [BITSTREAM=0..4].Set when automatic mode is entered. Automatic encode mode: used to detect when all banks have been flushed after the processing has completed (i.e. but request bank signals have been de-asserted by BBM). Automatic decode mode (BITSTREAM=DECODE): returns to 0 (IDLE) when automatic mode is left (BITSTREAM=COPR).Read 0x1: BBM is busy.Read 0x0: BBM is idle"; 70 bitstream 3 rw type(bitstream_status) "Bitstream buffer access control"; 71 bitstr_xfer_size 2 rw type(bitstr_xfer_size_status) "Defines the amount of data to be transferred per hardware request to the SIMCOP DMA. Bigger sizes lead to better SDRAM efficiency but prevents fine grained DMA transfer arbitration. This register is only used by hardware when BITSTREAM=ENCODE or BITSTREAM=DECODE."; 72 hw_seq_stop 1 wo type(hw_seq_stop_status) "Stop the hardware sequencer. This feature is typically used to recover from an error condition. Read's always return 0."; 73 hw_seq_start 1 wo type(hw_seq_start_status) "Start the hardware sequencer. Read's always return 0."; 74 }; 75 76 constants state_status width(1) "" { 77 STATE_0_r = 0 "Idle"; 78 STATE_1_r = 1 "Running"; 79 }; 80 81 register simcop_hwseq_status addr(base, 0x6C) "Hardware sequencer status register" { 82 hw_seq_step_counter 16 ro "Current step number"; 83 _ 15 mbz; 84 state 1 ro type(state_status) "Current state"; 85 }; 86 87 register simcop_hwseq_override addr(base, 0x70) "Hardware sequencer override control register. Bits in this register select what configuration register control a resource. 0: Resource controlled by hardware sequencer. Hardware uses the value from SIMCOP_HWSEQ_STEP_xx registers for the chosen resource 1: Resource controlled by software. Hardware uses the value from SIMCOP_HWSEQ_STEP_x_OVERRIDE registers for the chosen resource The bit field name matches the one of the resource.For example, IMX_A_D_OFST_OVR selects if" { 88 _ 13 mbz; 89 coeff_b 1 rw "See register description"; 90 coeff_a 1 rw "See register description"; 91 imbuff_h 1 rw "See register description"; 92 imbuff_g 1 rw "See register description"; 93 imbuff_f 1 rw "See register description"; 94 imbuff_e 1 rw "See register description"; 95 imbuff_d 1 rw "See register description"; 96 imbuff_c 1 rw "See register description"; 97 imbuff_b 1 rw "See register description"; 98 imbuff_a 1 rw "See register description"; 99 ldc_o_ofst_ovr 1 rw "See register description"; 100 rot_o_ofst_ovr 1 rw "See register description"; 101 rot_i_ofst_ovr 1 rw "See register description"; 102 nsf_io_ofst_ovr 1 rw "See register description"; 103 dct_f_ofst_ovr 1 rw "See register description"; 104 dct_s_ofst_ovr 1 rw "See register description"; 105 vlcdj_io_ofst_ovr 1 rw "See register description"; 106 imx_b_d_ofst_ovr 1 rw "See register description"; 107 imx_a_d_ofst_ovr 1 rw "See register description"; 108 }; 109 110 constants rot_o_ofst_status width(2) "" { 111 ROT_O_OFST_0 = 0 "EFGH"; 112 ROT_O_OFST_1 = 1 "FGHE"; 113 ROT_O_OFST_2 = 2 "GHEF"; 114 ROT_O_OFST_3 = 3 "HEFG"; 115 }; 116 117 constants rot_i_ofst_status width(2) "" { 118 ROT_I_OFST_0 = 0 "ABCD"; 119 ROT_I_OFST_1 = 1 "BCDA"; 120 ROT_I_OFST_2 = 2 "CDAB"; 121 ROT_I_OFST_3 = 3 "DABC"; 122 }; 123 124 constants dct_f_ofst_status width(3) "" { 125 DCT_F_OFST_0 = 0 "ABCD"; 126 DCT_F_OFST_1 = 1 "BCDG"; 127 DCT_F_OFST_2 = 2 "CDGH"; 128 DCT_F_OFST_3 = 3 "DGHA"; 129 DCT_F_OFST_4 = 4 "GHAB"; 130 DCT_F_OFST_5 = 5 "HABC"; 131 }; 132 133 constants dct_s_ofst_status width(2) "" { 134 DCT_S_OFST_0 = 0 "EF"; 135 DCT_S_OFST_1 = 1 "FG"; 136 DCT_S_OFST_2 = 2 "GH"; 137 DCT_S_OFST_3 = 3 "HE"; 138 }; 139 140 constants imx_b_d_ofst_status width(2) "" { 141 IMX_B_D_OFST_0 = 0 "ABCD"; 142 IMX_B_D_OFST_1 = 1 "CDEF"; 143 IMX_B_D_OFST_2 = 2 "EFGH"; 144 IMX_B_D_OFST_3 = 3 "GHAB"; 145 }; 146 147 constants dma_trigger_status width(3) "" { 148 DMA_TRIGGER_0_w = 0 "No effect"; 149 DMA_TRIGGER_0_r = 0 "No done pulse have been received since last non zero write into the DMA_TRIGGER register"; 150 DMA_TRIGGER_1_r = 1 "DONE pulses for channel 0 and 1 have been received"; 151 DMA_TRIGGER_1_w = 1 "Trigger channel 0 and 1. Clears all memorized done pulses for DMA."; 152 DMA_TRIGGER_2_w = 2 "Trigger channel 0, 1, 2. Clears all memorized done pulses for DMA."; 153 DMA_TRIGGER_2_r = 2 "DONE pulses for channel 0, 1 and 2 have been received"; 154 DMA_TRIGGER_3_r = 3 "DONE pulses for channel 0, 1, 2 and 3 have been received."; 155 DMA_TRIGGER_3_w = 3 "Trigger channel 0, 1, 2 and 3. Clears all memorized done pulses for DMA."; 156 DMA_TRIGGER_4_r = 4 "DONE pulse for channel 0 has been received"; 157 DMA_TRIGGER_4_w = 4 "Trigger channel 0. Clears all memorized done pulses for DMA."; 158 DMA_TRIGGER_5_w = 5 "Trigger channel 1. Clears all memorized done pulses for DMA."; 159 DMA_TRIGGER_5_r = 5 "DONE pulse for channel 1 has been received"; 160 DMA_TRIGGER_6_r = 6 "DONE pulse for channel 2 has been received"; 161 DMA_TRIGGER_6_w = 6 "Trigger channel 2. Clears all memorized done pulses for DMA."; 162 DMA_TRIGGER_7_w = 7 "Trigger channel 3. Clears all memorized done pulses for DMA."; 163 DMA_TRIGGER_7_r = 7 "DONE pulse for channel 3 has been received"; 164 }; 165 166 constants rot_a_trigger_status width(1) "" { 167 ROT_A_TRIGGER_0_w = 0 "No Effect"; 168 ROT_A_TRIGGER_0_r = 0 "No DONE pulse received since the last START pulse has been sent"; 169 ROT_A_TRIGGER_1_r = 1 "DONE pulse received"; 170 ROT_A_TRIGGER_1_w = 1 "Send a start pulse and clears the memorized done pulse"; 171 }; 172 173 register simcop_hwseq_step_ctrl_override addr(base, 0x74) "Hardware sequencer override register. Used to execute software sequences in parallel to hardware sequencing steps" { 174 _ 4 mbz; 175 rot_o_ofst 2 rw type(rot_o_ofst_status) "Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 176 rot_i_ofst 2 rw type(rot_i_ofst_status) "Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 177 _ 1 mbz; 178 dct_f_ofst 3 rw type(dct_f_ofst_status) "Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 179 dct_s_ofst 2 rw type(dct_s_ofst_status) "Controls DCT.S bus mapping to image buffers: 0x0000 0x1000"; 180 vlcdj_io_ofst 3 rw type(dct_f_ofst_status) "Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 181 imx_b_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 182 imx_a_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 183 _ 3 mbz; 184 dma_trigger 3 rw type(dma_trigger_status) "Software controlled START/DONE synchronization"; 185 rot_a_trigger 1 rw type(rot_a_trigger_status) "Software controlled START/DONE synchronization"; 186 nsf_trigger 1 rw type(rot_a_trigger_status) "Software controlled START/DONE synchronization"; 187 vlcdj_trigger 1 rw type(rot_a_trigger_status) "Software controlled START/DONE synchronization"; 188 dct_trigger 1 rw type(rot_a_trigger_status) "Software controlled START/DONE synchronization"; 189 ldc_trigger 1 rw type(rot_a_trigger_status) "Software controlled START/DONE synchronization"; 190 }; 191 192 constants imbuff_h_status width(4) "" { 193 IMBUFF_H_0 = 0 "Coprocessor bus"; 194 IMBUFF_H_1 = 1 "SIMCOP DMA"; 195 IMBUFF_H_2 = 2 "iMX A"; 196 IMBUFF_H_3 = 3 "iMX B"; 197 IMBUFF_H_4 = 4 "VLCDJ_IO"; 198 IMBUFF_H_5 = 5 "DCT_S"; 199 IMBUFF_H_6 = 6 "DCT_F"; 200 IMBUFF_H_7 = 7 "ROT_A_O"; 201 IMBUFF_H_8 = 8 "NSF_IO"; 202 IMBUFF_H_9 = 9 "LDC_O"; 203 }; 204 205 constants imbuff_f_status width(3) "" { 206 IMBUFF_F_0 = 0 "Coprocessor bus"; 207 IMBUFF_F_1 = 1 "SIMCOP DMA"; 208 IMBUFF_F_2 = 2 "iMX A"; 209 IMBUFF_F_3 = 3 "iMX B"; 210 IMBUFF_F_4 = 4 "DCT_S"; 211 IMBUFF_F_5 = 5 "NSF_IO"; 212 IMBUFF_F_6 = 6 "LDC_O"; 213 IMBUFF_F_7 = 7 "ROT_A_O"; 214 }; 215 216 constants imbuff_d_status width(3) "" { 217 IMBUFF_D_0 = 0 "Coprocessor bus"; 218 IMBUFF_D_1 = 1 "SIMCOP DMA"; 219 IMBUFF_D_2 = 2 "iMX A"; 220 IMBUFF_D_3 = 3 "iMX B"; 221 IMBUFF_D_4 = 4 "VLCDJ_IO"; 222 IMBUFF_D_5 = 5 "DCT_F"; 223 IMBUFF_D_6 = 6 "ROT_A_I"; 224 IMBUFF_D_7 = 7 "Reserved"; 225 }; 226 227 constants imbuff_b_status width(3) "" { 228 IMBUFF_B_0 = 0 "Coprocessor bus"; 229 IMBUFF_B_1 = 1 "SIMCOP DMA"; 230 IMBUFF_B_2 = 2 "iMX A IMBUFF"; 231 IMBUFF_B_3 = 3 "iMX B IMBUFF"; 232 IMBUFF_B_4 = 4 "VLCDJ_IO"; 233 IMBUFF_B_5 = 5 "DCT_F"; 234 IMBUFF_B_6 = 6 "ROT_A_I"; 235 IMBUFF_B_7 = 7 "Reserved"; 236 }; 237 238 register simcop_hwseq_step_switch_override addr(base, 0x78) "Hardware sequencer override register. Used to execute software sequences in parallel to hardware sequencing steps" { 239 imbuff_h 4 rw type(imbuff_h_status) "Switch for image buffer h"; 240 imbuff_g 4 rw type(imbuff_h_status) "Switch for image buffer g"; 241 _ 1 mbz; 242 imbuff_f 3 rw type(imbuff_f_status) "Switch for image buffer f"; 243 _ 1 mbz; 244 imbuff_e 3 rw type(imbuff_f_status) "Switch for image buffer e"; 245 _ 1 mbz; 246 imbuff_d 3 rw type(imbuff_d_status) "Switch for image buffer d"; 247 _ 1 mbz; 248 imbuff_c 3 rw type(imbuff_d_status) "Switch for image buffer c."; 249 _ 1 mbz; 250 imbuff_b 3 rw type(imbuff_b_status) "Switch for image buffer b."; 251 _ 1 mbz; 252 imbuff_a 3 rw type(imbuff_b_status) "Switch for image buffer a"; 253 }; 254 255 constants coeff_b_status width(3) "" { 256 COEFF_B_0 = 0 "Coprocessor bus"; 257 COEFF_B_1 = 1 "SIMCOP DMA"; 258 COEFF_B_2 = 2 "iMX A"; 259 COEFF_B_3 = 3 "iMX B"; 260 COEFF_B_4 = 4 "VLCDJ_IO"; 261 COEFF_B_5 = 5 "DCT_F"; 262 COEFF_B_6 = 6 "ROT A O"; 263 COEFF_B_7 = 7 "Reserved"; 264 }; 265 266 register simcop_hwseq_step_ctrl2_override addr(base, 0x7C) "Hardware sequencer override register. Used to execute software sequences in parallel to hardware sequencing steps" { 267 _ 20 mbz; 268 nsf2_io_ofst 2 rw type(dct_s_ofst_status) "Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000"; 269 ldc_o_ofst 2 rw type(rot_o_ofst_status) "Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 270 _ 1 mbz; 271 coeff_b 3 rw type(coeff_b_status) "Coefficient buffer b switch"; 272 _ 1 mbz; 273 coeff_a 3 rw type(imbuff_d_status) "Coefficient buffer a switch"; 274 }; 275 276 constants cpu_sync_status width(1) "" { 277 CPU_SYNC_0 = 0 "Disabled"; 278 CPU_SYNC_1 = 1 "Enabled."; 279 }; 280 281 constants dma_ofst_status width(3) "" { 282 DMA_OFST_0 = 0 "ABCDEFGH"; 283 DMA_OFST_1 = 1 "BCDEFGHA"; 284 DMA_OFST_2 = 2 "CDEFGHAB"; 285 DMA_OFST_3 = 3 "DEFGHABC"; 286 DMA_OFST_4 = 4 "EFGHABCD"; 287 DMA_OFST_5 = 5 "FGHABCDE"; 288 DMA_OFST_6 = 6 "GHABCDEF"; 289 DMA_OFST_7 = 7 "HABCDEFG"; 290 }; 291 292 constants next_status width(2) "" { 293 NEXT_0 = 0 "Step 0"; 294 NEXT_1 = 1 "Step 1"; 295 NEXT_2 = 2 "Step 2"; 296 NEXT_3 = 3 "Step 3"; 297 }; 298 299 constants dma_sync_status width(3) "" { 300 DMA_SYNC_0 = 0 "Disabled"; 301 DMA_SYNC_1 = 1 "Channel 0 and 1"; 302 DMA_SYNC_2 = 2 "Channel 0, 1, 2"; 303 DMA_SYNC_3 = 3 "Channel 0, 1, 2 and 3"; 304 DMA_SYNC_4 = 4 "Channel 0"; 305 DMA_SYNC_5 = 5 "Channel 1"; 306 DMA_SYNC_6 = 6 "Channel 2"; 307 DMA_SYNC_7 = 7 "Channel 3"; 308 }; 309 310 constants nsf_sync_status width(1) "" { 311 NSF_SYNC_0 = 0 "Disabled"; 312 NSF_SYNC_1 = 1 "Enabled"; 313 }; 314 315 register simcop_hwseq_step_ctrl_i_0 addr(base, 0x80) "Hardware sequencer step control register" { 316 cpu_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline."; 317 dma_ofst 3 rw type(dma_ofst_status) "Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000"; 318 rot_o_ofst 2 rw type(rot_o_ofst_status) "Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 319 rot_i_ofst 2 rw type(rot_i_ofst_status) "Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 320 _ 1 mbz; 321 dct_f_ofst 3 rw type(dct_f_ofst_status) "Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 322 dct_s_ofst 2 rw type(dct_s_ofst_status) "Controls DCT.S bus mapping to image buffers: 0x0000 0x1000"; 323 vlcdj_io_ofst 3 rw type(dct_f_ofst_status) "Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 324 imx_b_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 325 imx_a_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 326 next 2 rw type(next_status) "Next channel in the sync chain"; 327 _ 1 mbz; 328 dma_sync 3 rw type(dma_sync_status) "Enable hardware synchronization with the SIMCOP DMA"; 329 rot_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the ROT #a module"; 330 nsf_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the NSF module"; 331 vlcdj_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the VLCDJ module"; 332 dct_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the DCT module"; 333 ldc_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the LDC module"; 334 }; 335 336 register simcop_hwseq_step_ctrl_i_1 addr(base, 0x90) "Hardware sequencer step control register" { 337 cpu_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline."; 338 dma_ofst 3 rw type(dma_ofst_status) "Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000"; 339 rot_o_ofst 2 rw type(rot_o_ofst_status) "Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 340 rot_i_ofst 2 rw type(rot_i_ofst_status) "Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 341 _ 1 mbz; 342 dct_f_ofst 3 rw type(dct_f_ofst_status) "Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 343 dct_s_ofst 2 rw type(dct_s_ofst_status) "Controls DCT.S bus mapping to image buffers: 0x0000 0x1000"; 344 vlcdj_io_ofst 3 rw type(dct_f_ofst_status) "Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 345 imx_b_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 346 imx_a_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 347 next 2 rw type(next_status) "Next channel in the sync chain"; 348 _ 1 mbz; 349 dma_sync 3 rw type(dma_sync_status) "Enable hardware synchronization with the SIMCOP DMA"; 350 rot_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the ROT #a module"; 351 nsf_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the NSF module"; 352 vlcdj_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the VLCDJ module"; 353 dct_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the DCT module"; 354 ldc_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the LDC module"; 355 }; 356 357 register simcop_hwseq_step_ctrl_i_2 addr(base, 0xA0) "Hardware sequencer step control register" { 358 cpu_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline."; 359 dma_ofst 3 rw type(dma_ofst_status) "Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000"; 360 rot_o_ofst 2 rw type(rot_o_ofst_status) "Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 361 rot_i_ofst 2 rw type(rot_i_ofst_status) "Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 362 _ 1 mbz; 363 dct_f_ofst 3 rw type(dct_f_ofst_status) "Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 364 dct_s_ofst 2 rw type(dct_s_ofst_status) "Controls DCT.S bus mapping to image buffers: 0x0000 0x1000"; 365 vlcdj_io_ofst 3 rw type(dct_f_ofst_status) "Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 366 imx_b_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 367 imx_a_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 368 next 2 rw type(next_status) "Next channel in the sync chain"; 369 _ 1 mbz; 370 dma_sync 3 rw type(dma_sync_status) "Enable hardware synchronization with the SIMCOP DMA"; 371 rot_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the ROT #a module"; 372 nsf_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the NSF module"; 373 vlcdj_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the VLCDJ module"; 374 dct_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the DCT module"; 375 ldc_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the LDC module"; 376 }; 377 378 register simcop_hwseq_step_ctrl_i_3 addr(base, 0xB0) "Hardware sequencer step control register" { 379 cpu_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the CPU so that it can be used for some processing on in the macroblock pipeline."; 380 dma_ofst 3 rw type(dma_ofst_status) "Controls DMA bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000"; 381 rot_o_ofst 2 rw type(rot_o_ofst_status) "Controls ROT.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 382 rot_i_ofst 2 rw type(rot_i_ofst_status) "Controls ROT_I bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 383 _ 1 mbz; 384 dct_f_ofst 3 rw type(dct_f_ofst_status) "Controls DCT.F bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 385 dct_s_ofst 2 rw type(dct_s_ofst_status) "Controls DCT.S bus mapping to image buffers: 0x0000 0x1000"; 386 vlcdj_io_ofst 3 rw type(dct_f_ofst_status) "Controls VLCDJ IO data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 387 imx_b_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX B data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 388 imx_a_d_ofst 2 rw type(imx_b_d_ofst_status) "Controls iMX A data bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 389 next 2 rw type(next_status) "Next channel in the sync chain"; 390 _ 1 mbz; 391 dma_sync 3 rw type(dma_sync_status) "Enable hardware synchronization with the SIMCOP DMA"; 392 rot_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the ROT #a module"; 393 nsf_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the NSF module"; 394 vlcdj_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the VLCDJ module"; 395 dct_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the DCT module"; 396 ldc_sync 1 rw type(nsf_sync_status) "Enable hardware synchronization with the LDC module"; 397 }; 398 399 register simcop_hwseq_step_switch_i_0 addr(base, 0x84) "Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." { 400 imbuff_h 4 rw type(imbuff_h_status) "Switch for image buffer h"; 401 imbuff_g 4 rw type(imbuff_h_status) "Switch for image buffer g"; 402 _ 1 mbz; 403 imbuff_f 3 rw type(imbuff_f_status) "Switch for image buffer f"; 404 _ 1 mbz; 405 imbuff_e 3 rw type(imbuff_f_status) "Switch for image buffer e"; 406 _ 1 mbz; 407 imbuff_d 3 rw type(imbuff_d_status) "Switch for image buffer d"; 408 _ 1 mbz; 409 imbuff_c 3 rw type(imbuff_d_status) "Switch for image buffer c."; 410 _ 1 mbz; 411 imbuff_b 3 rw type(imbuff_b_status) "Switch for image buffer b."; 412 _ 1 mbz; 413 imbuff_a 3 rw type(imbuff_b_status) "Switch for image buffer a"; 414 }; 415 416 register simcop_hwseq_step_switch_i_1 addr(base, 0x94) "Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." { 417 imbuff_h 4 rw type(imbuff_h_status) "Switch for image buffer h"; 418 imbuff_g 4 rw type(imbuff_h_status) "Switch for image buffer g"; 419 _ 1 mbz; 420 imbuff_f 3 rw type(imbuff_f_status) "Switch for image buffer f"; 421 _ 1 mbz; 422 imbuff_e 3 rw type(imbuff_f_status) "Switch for image buffer e"; 423 _ 1 mbz; 424 imbuff_d 3 rw type(imbuff_d_status) "Switch for image buffer d"; 425 _ 1 mbz; 426 imbuff_c 3 rw type(imbuff_d_status) "Switch for image buffer c."; 427 _ 1 mbz; 428 imbuff_b 3 rw type(imbuff_b_status) "Switch for image buffer b."; 429 _ 1 mbz; 430 imbuff_a 3 rw type(imbuff_b_status) "Switch for image buffer a"; 431 }; 432 433 register simcop_hwseq_step_switch_i_2 addr(base, 0xA4) "Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." { 434 imbuff_h 4 rw type(imbuff_h_status) "Switch for image buffer h"; 435 imbuff_g 4 rw type(imbuff_h_status) "Switch for image buffer g"; 436 _ 1 mbz; 437 imbuff_f 3 rw type(imbuff_f_status) "Switch for image buffer f"; 438 _ 1 mbz; 439 imbuff_e 3 rw type(imbuff_f_status) "Switch for image buffer e"; 440 _ 1 mbz; 441 imbuff_d 3 rw type(imbuff_d_status) "Switch for image buffer d"; 442 _ 1 mbz; 443 imbuff_c 3 rw type(imbuff_d_status) "Switch for image buffer c."; 444 _ 1 mbz; 445 imbuff_b 3 rw type(imbuff_b_status) "Switch for image buffer b."; 446 _ 1 mbz; 447 imbuff_a 3 rw type(imbuff_b_status) "Switch for image buffer a"; 448 }; 449 450 register simcop_hwseq_step_switch_i_3 addr(base, 0xB4) "Image buffer switch control. The configuration of step #0 is used when hardware sequencer is idle." { 451 imbuff_h 4 rw type(imbuff_h_status) "Switch for image buffer h"; 452 imbuff_g 4 rw type(imbuff_h_status) "Switch for image buffer g"; 453 _ 1 mbz; 454 imbuff_f 3 rw type(imbuff_f_status) "Switch for image buffer f"; 455 _ 1 mbz; 456 imbuff_e 3 rw type(imbuff_f_status) "Switch for image buffer e"; 457 _ 1 mbz; 458 imbuff_d 3 rw type(imbuff_d_status) "Switch for image buffer d"; 459 _ 1 mbz; 460 imbuff_c 3 rw type(imbuff_d_status) "Switch for image buffer c."; 461 _ 1 mbz; 462 imbuff_b 3 rw type(imbuff_b_status) "Switch for image buffer b."; 463 _ 1 mbz; 464 imbuff_a 3 rw type(imbuff_b_status) "Switch for image buffer a"; 465 }; 466 467 register simcop_hwseq_step_imx_ctrl_i_0 addr(base, 0x88) "Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." { 468 imx_b_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX B module"; 469 _ 2 mbz; 470 imx_b_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 471 imx_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX A module"; 472 _ 2 mbz; 473 imx_a_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 474 }; 475 476 register simcop_hwseq_step_imx_ctrl_i_1 addr(base, 0x98) "Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." { 477 imx_b_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX B module"; 478 _ 2 mbz; 479 imx_b_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 480 imx_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX A module"; 481 _ 2 mbz; 482 imx_a_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 483 }; 484 485 register simcop_hwseq_step_imx_ctrl_i_2 addr(base, 0xA8) "Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." { 486 imx_b_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX B module"; 487 _ 2 mbz; 488 imx_b_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 489 imx_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX A module"; 490 _ 2 mbz; 491 imx_a_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 492 }; 493 494 register simcop_hwseq_step_imx_ctrl_i_3 addr(base, 0xB8) "Hardware sequencer step control register The configuration of step #0 is used when hardware sequencer is idle." { 495 imx_b_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX B module"; 496 _ 2 mbz; 497 imx_b_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[31] IMX_B_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 498 imx_a_sync 1 rw type(cpu_sync_status) "Enable hardware synchronization with the iMX A module"; 499 _ 2 mbz; 500 imx_a_start 13 rw "This register is only used whenSIMCOP_HWSEQ_STEP_IMX_CTRL_i[15] IMX_A_SYNC=1. It contains the address, in 16-bit words, of the first instruction iMX will execute when it gets started."; 501 }; 502 503 register simcop_hwseq_step_ctrl2_i_0 addr(base, 0x8C) "Hardware sequencer step control register" { 504 _ 20 mbz; 505 nsf2_io_ofst 2 rw type(dct_s_ofst_status) "Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000"; 506 ldc_o_ofst 2 rw type(rot_o_ofst_status) "Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 507 _ 1 mbz; 508 coeff_b 3 rw type(coeff_b_status) "Coefficient buffer b switch"; 509 _ 1 mbz; 510 coeff_a 3 rw type(imbuff_d_status) "Coefficient buffer a switch"; 511 }; 512 513 register simcop_hwseq_step_ctrl2_i_1 addr(base, 0x9C) "Hardware sequencer step control register" { 514 _ 20 mbz; 515 nsf2_io_ofst 2 rw type(dct_s_ofst_status) "Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000"; 516 ldc_o_ofst 2 rw type(rot_o_ofst_status) "Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 517 _ 1 mbz; 518 coeff_b 3 rw type(coeff_b_status) "Coefficient buffer b switch"; 519 _ 1 mbz; 520 coeff_a 3 rw type(imbuff_d_status) "Coefficient buffer a switch"; 521 }; 522 523 register simcop_hwseq_step_ctrl2_i_2 addr(base, 0xAC) "Hardware sequencer step control register" { 524 _ 20 mbz; 525 nsf2_io_ofst 2 rw type(dct_s_ofst_status) "Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000"; 526 ldc_o_ofst 2 rw type(rot_o_ofst_status) "Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 527 _ 1 mbz; 528 coeff_b 3 rw type(coeff_b_status) "Coefficient buffer b switch"; 529 _ 1 mbz; 530 coeff_a 3 rw type(imbuff_d_status) "Coefficient buffer a switch"; 531 }; 532 533 register simcop_hwseq_step_ctrl2_i_3 addr(base, 0xBC) "Hardware sequencer step control register" { 534 _ 20 mbz; 535 nsf2_io_ofst 2 rw type(dct_s_ofst_status) "Controls NSF_IO bus mapping to image buffers: 0x0000 0x1000"; 536 ldc_o_ofst 2 rw type(rot_o_ofst_status) "Controls LDC.O bus mapping to image buffers: 0x0000 0x1000 0x2000 0x3000"; 537 _ 1 mbz; 538 coeff_b 3 rw type(coeff_b_status) "Coefficient buffer b switch"; 539 _ 1 mbz; 540 coeff_a 3 rw type(imbuff_d_status) "Coefficient buffer a switch"; 541 }; 542};