1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_hdq_1_wire.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_hdq_1_wire msbfirst ( addr base ) "" {
29    
30    
31    register hdq_revision ro addr(base, 0x0) "This register contains the IP revision code" type(uint32);
32    
33    register hdq_tx_data addr(base, 0x4) "This register contains the data to be transmitted." {
34        _ 24 mbz;
35        tx_data 8 rw "Transmit data (used in both HDQ and 1-Wire modes)";
36    };
37    
38    register hdq_rx_data addr(base, 0x8) "This register contains the data to be received." {
39        _ 24 mbz;
40        rx_data 8 ro "Receive data (used in both HDQ and 1-Wire modes)";
41    };
42    
43    register hdq_ctrl_status addr(base, 0xC) "This register provides status information about the module." {
44        _ 24 mbz;
45        one_wire_single_bit 1 rw "Single-bit mode for 1-Wire0x0: Disabled 0x1: Enabled";
46        interruptmask 1 rw "Interrupt masking bit0x0: Interrupts disable 0x1: Interrupts enable";
47        clockenable 1 rw "Power-down mode bit0x0: Clock disable (power down)0x1: Clock enable";
48        go 1 rw "Go bit. Write 1 to start the appropriate operation. Bit returns to 0 after the operation is complete.";
49        presencedetect 1 ro "Slave presence indicator. Actual only just after initialization time-out. Used in 1-Wire mode. Read-only flag.0x0: No slave detected0x1: Slave detected";
50        initialization 1 rw "Write 1 to send initialization pulse. Bit returns to 0 after pulse is sent.";
51        dir 1 rw "DIR bit, determines if next command is read or write0x0: Write 0x1: Read";
52        mode 1 rw "Mode selection bit0x0: HDQ mode 0x1: 1-Wire mode";
53    };
54    
55    register hdq_int_status addr(base, 0x10) "This register controls interrupts status" {
56        _ 29 mbz;
57        txcomplete 1 ro "TX-complete interrupt flag.Set to 1 if cause of interrupt. Set to 0 when register read.";
58        rxcomplete 1 ro "Read-complete interrupt flag.Set to 1 if cause of interrupt. Set to 0 when register read.";
59        timeout 1 ro "Presence detect/timeout interrupt flag.In 1-Wire mode, set to 1 if slave's presence detected. In HDQ mode, set to 1 if timeout on read occurs. Set to 0 when register read.";
60    };
61    
62    register hdq_sysconfig addr(base, 0x14) "This register controls various bits" {
63        _ 30 mbz;
64        softreset 1 rw "Start soft reset sequence.0x0: Disabled 0x1: Enabled";
65        autoidle 1 rw "Interconnect idle.0x0: Module clock is free-running. 0x1: Module is in power saving mode: Clock is running only when module is accessed or inside logic is in function to process events.";
66    };
67    
68    register hdq_sysstatus addr(base, 0x18) "This register monitors the reset sequence." {
69        _ 31 mbz;
70        resetdone 1 ro "Reset monitoring.0x0: The module is currently performing its reset. When the module is in power-down mode, set to 0 to indicate this fact. 0x1: The module has finished its reset.";
71    };
72};