1/*
2 * Copyright (c) 2012, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_gpio.dev
12 *
13 * DESCRIPTION: OMAP44xx General-Purpose I/O blocks.  The 4460 has 6
14 * of these. 
15 *
16 * This is derived from:
17 *
18 * OMAP4460 Multimedia Device Silicon Revision 1.x Technical Reference
19 * Manual Version Q, in particular Section 25.6
20 *
21 */
22
23device omap44xx_gpio msbfirst ( addr base ) "OMAP44xx Gen. Purpose I/O" {
24
25    register revision ro addr(base, 0x0000) "IP revision number" type(uint32);
26
27    constants idle_m width(2) "Idle mode" {
28	im_force	= 0x0 "Force idle";
29	im_none		= 0x1 "No idle";
30	im_smart	= 0x2 "Smart idle";
31	im_smartw	= 0x3 "Smart idle wakeup";
32    };
33    register sysconfig rw addr(base, 0x0010) "System configuration" {
34	_		27;
35	idlemode	2 type(idle_m)	"Idle mode";
36	enawakeup	1		"Wake-up enable";
37	softreset	1		"Software reset";
38	autoidle	1		"OCP clock gating control";
39    };
40
41    register irqstatus_raw_0 rw addr(base, 0x0024) 
42	"Per-event raw interrupt status vector (1st line)" type(uint32);
43
44    register irqstatus_raw_1 rw addr(base, 0x0028)
45	"Per-event raw interrupt status vector (2nd line)" type(uint32);
46
47    register irqstatus_0 rw addr(base, 0x002C) 
48	"Per-event interrupt status vector (1st line)" type(uint32);
49
50    register irqstatus_1 rw addr(base, 0x0030) 
51	"Per-event interrupt status vector (2nd line)" type(uint32);
52
53    register irqstatus_set_0 rw addr(base, 0x0034)
54	"Interrupt enable set vector (1st line)" type(uint32);
55        
56    register irqstatus_set_1 rw addr(base, 0x0038) 
57	"Interrupt enable set vector (2nd line)" type(uint32);
58
59    register irqstatus_clr_0 rw addr(base, 0x003C)
60	"Interrupt enable clear vector (1st line)" type(uint32);
61
62    register irqstatus_clr_1 rw addr(base, 0x0040)
63	"Interrupt enable clear vector (1st line)" type(uint32);
64
65    register irqwaken_0 rw addr(base, 0x0044)
66	"Per-event wakeup enable set vector (1st line)" type(uint32);
67
68    register irqwaken_1 rw addr(base, 0x0048)
69	"Per-event wakeup enable set vector (2nd line)" type(uint32);
70
71    register sysstatus ro addr(base, 0x0114) "System status" {
72	_		31;
73	resetdone	1		"Reset is complete";
74    };
75
76    register irqstatus1 rw addr(base, 0x0118) 
77	"Interrupt status (legacy) for 1st line" type(uint32);
78
79    register irqenable1 rw addr(base, 0x011C) 
80	"Interrupt enable (legacy) for 1st line" type(uint32);
81
82    register wakeupenable rw addr(base, 0x0120) 
83	"Wake-up enable (legacy) for 1st line" type(uint32);
84
85    register irqstatus2 rw addr(base, 0x0128)
86	"Interrupt status (legacy) for 2nd line" type(uint32);
87
88    register irqenable2 rw addr(base, 0x012C) 
89	"Interrupt enable (legacy) for 2nd line" type(uint32);
90
91    register ctrl rw addr(base, 0x0130) "Control" {
92	_		29;
93	gatingratio	2	"Clock gating ratio (1<<x)";
94	disablemodule	1	"Disable module; gate clocks";
95    };
96    
97    register oe rw addr(base, 0x0134) 
98	"Output enable" type(uint32);
99
100    register datain ro addr(base, 0x0138) 
101	"Data input" type(uint32);
102
103    register dataout rw addr(base, 0x013C) 
104	"Data output" type(uint32);
105
106    register leveldetect0 rw addr(base, 0x0140) 
107	"Detect low level" type(uint32);
108
109    register leveldetect1 rw addr(base, 0x0144) 
110	"Detect high level" type(uint32);
111
112    register risingdetect rw addr(base, 0x0148) 
113	"Detect rising edge" type(uint32);
114
115    register fallingdetect rw addr(base, 0x014C) 
116	"Detect falling edge" type(uint32);
117
118    register debouncenable rw addr(base, 0x0150) 
119	"Debounce enable" type(uint32);
120
121    register debouncingtime rw addr(base, 0x0154) "Debouncing time" {
122	_	24;
123	time	8	"Debouncing time in 31us steps";
124    };
125
126    register clearirqenable1 rw addr(base, 0x0160) 
127	"Clear interrupt enable - legacy mode" type(uint32);
128
129    register setirqenable1 rw addr(base, 0x0164) 
130	"Set interrupt enable - legacy mode" type(uint32);
131
132    register clearirqenable2 rw addr(base, 0x0170) 
133	"Clear interrupt enable" type(uint32);
134
135    register setirqenable2 rw addr(base, 0x0174)
136	"Set interrupt enable" type(uint32);
137
138    register clearwkupena rw addr(base, 0x0180) 
139	"Clear Wakeup enable" type(uint32);
140    
141    register setwkuena rw addr(base, 0x0184) 
142	"Set wakeup enable" type(uint32);
143
144    register cleardataout rw addr(base, 0x0190) 
145	"Clear data out" type(uint32);
146
147    register setdataout rw addr(base, 0x0194) 
148	"Set data out" type(uint32);
149
150};
151