1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_emu_prm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_emu_prm msbfirst ( addr base ) "" { 29 30 31 constants emu_bank_onstate_status width(2) "" { 32 EMU_BANK_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON."; 33 }; 34 35 constants powerstate_status width(2) "" { 36 POWERSTATE_0_r = 0 "OFF state"; 37 }; 38 39 register pm_emu_pwrstctrl addr(base, 0x0) "This register controls the EMU power state to reach upon a domain sleep transition" { 40 _ 14 mbz; 41 emu_bank_onstate 2 ro type(emu_bank_onstate_status) "EMU memory state when domain is ON."; 42 _ 14 mbz; 43 powerstate 2 ro type(powerstate_status) "Power state control"; 44 }; 45 46 constants lastpowerstateentered_status width(2) "" { 47 LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF"; 48 LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION"; 49 LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE"; 50 LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE"; 51 }; 52 53 constants intransition_status width(1) "" { 54 INTRANSITION_0_r = 0 "No ongoing transition on power domain"; 55 INTRANSITION_1_r = 1 "Power domain transition is in progress."; 56 }; 57 58 constants emu_bank_statest_status width(2) "" { 59 EMU_BANK_STATEST_0_r = 0 "Memory is OFF"; 60 EMU_BANK_STATEST_1_r = 1 "Reserved"; 61 EMU_BANK_STATEST_2_r = 2 "Reserved"; 62 EMU_BANK_STATEST_3_r = 3 "Memory is ON It is supplied by WKUP LDO"; 63 }; 64 65 constants logicstatest_status width(1) "" { 66 LOGICSTATEST_0_r = 0 "Logic in domain is OFF"; 67 LOGICSTATEST_1_r = 1 "Logic in domain is ON"; 68 }; 69 70 constants powerstatest_status width(2) "" { 71 POWERSTATEST_0_r = 0 "Power domain is OFF"; 72 POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE"; 73 }; 74 75 register pm_emu_pwrstst addr(base, 0x4) "This register provides a status on the EMU domain current power state. [warm reset insensitive]" { 76 _ 6 mbz; 77 lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only."; 78 _ 3 mbz; 79 intransition 1 ro type(intransition_status) "Domain transition status"; 80 _ 14 mbz; 81 emu_bank_statest 2 ro type(emu_bank_statest_status) "EMU memory bank state status"; 82 _ 1 mbz; 83 logicstatest 1 ro type(logicstatest_status) "Logic state status"; 84 powerstatest 2 ro type(powerstatest_status) "Current power state status"; 85 }; 86 87 constants lostmem_emu_bank_status width(1) "" { 88 LOSTMEM_EMU_BANK_0 = 0 "Context has been maintained"; 89 LOSTMEM_EMU_BANK_1 = 1 "Context has been lost"; 90 }; 91 92 register rm_emu_debugss_context addr(base, 0x24) "This register contains dedicated DEBUGSS context statuses. [warm reset insensitive]" { 93 _ 23 mbz; 94 lostmem_emu_bank 1 rw1c type(lostmem_emu_bank_status) "Specify if memory-based context in EMU_BANK memory bank has been lost due to a previous power transition or other reset source."; 95 _ 7 mbz; 96 lostcontext_dff 1 rw1c type(lostmem_emu_bank_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of EMU_RST signal)"; 97 }; 98};