1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_device_prm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_device_prm msbfirst ( addr base ) "" { 29 30 31 constants rst_global_cold_software_status width(1) "" { 32 RST_GLOBAL_COLD_software_0 = 0 "Global COLD software reset is cleared."; 33 RST_GLOBAL_COLD_software_1 = 1 "Triggers a global COLD software reset. The software must ensure the SDRAM is properly put in sef-refresh mode before applying this reset."; 34 }; 35 36 constants rst_global_warm_software_status width(1) "" { 37 RST_GLOBAL_WARM_software_0 = 0 "Global warm software reset is cleared."; 38 RST_GLOBAL_WARM_software_1 = 1 "Triggers a global warm software reset."; 39 }; 40 41 register prm_rstctrl addr(base, 0x0) "Global software cold and warm reset control. This register is auto-cleared. Only write 1 is possible. A read returns 0 only." { 42 _ 30 mbz; 43 rst_global_cold_software 1 rw type(rst_global_cold_software_status) "Global COLD software reset control. This bit is reset only upon a global cold source of reset."; 44 rst_global_warm_software 1 rw type(rst_global_warm_software_status) "Global WARM software reset control. This bit is reset upon any global source of reset (warm and cold)."; 45 }; 46 47 constants c2c_rst_status width(1) "" { 48 C2C_RST_0 = 0 "No C2C warm reset."; 49 C2C_RST_1 = 1 "C2C warm reset has occurred."; 50 }; 51 52 constants icepick_rst_status width(1) "" { 53 ICEPICK_RST_0 = 0 "No ICEPICK reset."; 54 ICEPICK_RST_1 = 1 "IcePick reset has occurred."; 55 }; 56 57 constants vdd_core_volt_mgr_rst_status width(1) "" { 58 VDD_CORE_VOLT_MGR_RST_0 = 0 "No VDD_CORE voltage manager reset."; 59 VDD_CORE_VOLT_MGR_RST_1 = 1 "VDD_CORE voltage manager reset has occurred."; 60 }; 61 62 constants vdd_iva_volt_mgr_rst_status width(1) "" { 63 VDD_IVA_VOLT_MGR_RST_0 = 0 "No VDD_IVA voltage manager reset."; 64 VDD_IVA_VOLT_MGR_RST_1 = 1 "VDD_IVA voltage manager reset has occurred."; 65 }; 66 67 constants vdd_mpu_volt_mgr_rst_status width(1) "" { 68 VDD_MPU_VOLT_MGR_RST_0 = 0 "No VDD_MPU voltage manager reset."; 69 VDD_MPU_VOLT_MGR_RST_1 = 1 "VDD_MPU voltage manager reset has occurred."; 70 }; 71 72 constants external_warm_rst_status width(1) "" { 73 EXTERNAL_WARM_RST_0 = 0 "No global warm reset."; 74 EXTERNAL_WARM_RST_1 = 1 "Global external warm reset has occurred."; 75 }; 76 77 constants mpu_wdt_rst_status width(1) "" { 78 MPU_WDT_RST_0 = 0 "No MPU watchdog reset."; 79 MPU_WDT_RST_1 = 1 "MPU wachtdog reset has occurred."; 80 }; 81 82 constants global_warm_sw_rst_status width(1) "" { 83 GLOBAL_WARM_SW_RST_0 = 0 "No global warm software reset"; 84 GLOBAL_WARM_SW_RST_1 = 1 "Global warm software reset has occurred."; 85 }; 86 87 constants global_cold_rst_status width(1) "" { 88 GLOBAL_COLD_RST_0 = 0 "No power-on reset."; 89 GLOBAL_COLD_RST_1 = 1 "Power-on reset has occurred."; 90 }; 91 92 register prm_rstst addr(base, 0x4) "This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" { 93 _ 21 mbz; 94 c2c_rst 1 rw1c type(c2c_rst_status) "C2C warm reset event. This is a source of global warm reset."; 95 icepick_rst 1 rw1c type(icepick_rst_status) "IcePick reset event. This is a source of global warm reset initiated by the emulation."; 96 vdd_core_volt_mgr_rst 1 rw1c type(vdd_core_volt_mgr_rst_status) "VDD_CORE voltage manager reset event This is a source of global WARM reset."; 97 vdd_iva_volt_mgr_rst 1 rw1c type(vdd_iva_volt_mgr_rst_status) "VDD_IVA voltage manager reset event This is a source of global WARM reset."; 98 vdd_mpu_volt_mgr_rst 1 rw1c type(vdd_mpu_volt_mgr_rst_status) "VDD_MPU voltage manager reset event This is a source of global WARM reset."; 99 external_warm_rst 1 rw1c type(external_warm_rst_status) "External warm reset event"; 100 _ 1 mbz; 101 mpu_wdt_rst 1 rw1c type(mpu_wdt_rst_status) "MPU Watchdog timer reset event. This is a source of global WARM reset."; 102 _ 1 mbz; 103 global_warm_sw_rst 1 rw1c type(global_warm_sw_rst_status) "Global warm software reset event"; 104 global_cold_rst 1 rw1c type(global_cold_rst_status) "Power-on (cold) reset event"; 105 }; 106 107 constants rsttime2_status width(5) "" { 108 RSTTIME2_0 = 0 "Reserved"; 109 }; 110 111 register prm_rsttime addr(base, 0x8) "Reset duration control. [warm reset insensitive]" { 112 _ 17 mbz; 113 rsttime2 5 rw type(rsttime2_status) "(Power domain) reset duration 2 (number of RM.SYSCLK clock cycles)"; 114 rsttime1 10 rw type(rsttime2_status) "(Global) reset duration 1 (number of Func_32k.clk clock cycles)"; 115 }; 116 117 constants clkreq_cond_status width(3) "" { 118 CLKREQ_COND_0 = 0 "CLKREQ is never de-asserted"; 119 CLKREQ_COND_1 = 1 "CLKREQ is de-asserted when system clock is not required by any function in the device and if all voltage domains are in OFF state."; 120 CLKREQ_COND_2 = 2 "CLKREQ is de-asserted when system clock is not required by any function in the device and if all voltage domains are in RET or OFF state."; 121 CLKREQ_COND_3 = 3 "CLKREQ is de-asserted when system clock is not required by any function in the device and if all voltage domains are in SLEEP or RET or OFF state."; 122 CLKREQ_COND_4 = 4 "CLKREQ is de-asserted when system clock is not required by any function in the device. This is designed for low-power use-cases using the DPLL cascading scheme (ex: MP3)"; 123 CLKREQ_COND_5_r = 5 "Reserved"; 124 CLKREQ_COND_6_r = 6 "Reserved"; 125 CLKREQ_COND_7_r = 7 "Reserved"; 126 }; 127 128 register prm_clkreqctrl addr(base, 0xC) "This register allows controlling the CLKREQ signal towards SCRM." { 129 _ 29 mbz; 130 clkreq_cond 3 rw type(clkreq_cond_status) "Control upon which condition CLKREQ signal is de-asserted."; 131 }; 132 133 constants vdd_iva_i2c_disable_status width(1) "" { 134 VDD_IVA_I2C_DISABLE_0 = 0 "Normal mode: I2C is enabled."; 135 VDD_IVA_I2C_DISABLE_1 = 1 "Debug mode: I2C is disabled."; 136 }; 137 138 constants vdd_iva_presence_status width(1) "" { 139 VDD_IVA_PRESENCE_0 = 0 "IVA voltage is not present as an individual voltage: IVA voltage is merged with MPU voltage if VDD_MPU_presence=1. IVA voltage is merged with CORE voltage if VDD_MPU_presence=0."; 140 VDD_IVA_PRESENCE_1 = 1 "IVA voltage is present on the device."; 141 }; 142 143 constants vdd_mpu_presence_status width(1) "" { 144 VDD_MPU_PRESENCE_0 = 0 "MPU voltage is not present as an individual voltage: MPU voltage is merged with IVA voltage if VDD_IVA_presence=1. MPU voltage is merged with CORE voltage if VDD_IVA_presence=0."; 145 VDD_MPU_PRESENCE_1 = 1 "MPU voltage is present on the device."; 146 }; 147 148 constants auto_ctrl_vdd_iva_l_status width(2) "" { 149 AUTO_CTRL_VDD_IVA_L_0 = 0 "Voltage domain transitions are disabled."; 150 AUTO_CTRL_VDD_IVA_L_1 = 1 "Voltage domain transitions to SLEEP are enabled."; 151 AUTO_CTRL_VDD_IVA_L_2 = 2 "Voltage domain transitions to RET are enabled."; 152 AUTO_CTRL_VDD_IVA_L_3_r = 3 "reserved"; 153 }; 154 155 register prm_voltctrl addr(base, 0x10) "This register provides voltage domain management controls." { 156 _ 17 mbz; 157 vdd_iva_i2c_disable 1 rw type(vdd_iva_i2c_disable_status) "This bit allows disabling I2C interface with powerIC for IVA voltage (for debug purpose only). [warm reset insensitive]"; 158 vdd_mpu_i2c_disable 1 rw type(vdd_iva_i2c_disable_status) "This bit allows disabling I2C interface with powerIC for MPU voltage (for debug purpose only). [warm reset insensitive]"; 159 vdd_core_i2c_disable 1 rw type(vdd_iva_i2c_disable_status) "This bit allows disabling I2C interface with powerIC for CORE voltage (for debug purpose only). [warm reset insensitive]"; 160 _ 2 mbz; 161 vdd_iva_presence 1 rw type(vdd_iva_presence_status) "This bit control the presence of IVA voltage in device. [warm reset insensitive]"; 162 vdd_mpu_presence 1 rw type(vdd_mpu_presence_status) "This bit control the presence of MPU voltage in device. [warm reset insensitive]"; 163 _ 2 mbz; 164 auto_ctrl_vdd_iva_l 2 rw type(auto_ctrl_vdd_iva_l_status) "This bit field specifies the state to which the hardware can automatically transition the VDD_IVA_L voltage domain."; 165 auto_ctrl_vdd_mpu_l 2 rw type(auto_ctrl_vdd_iva_l_status) "This bit field specifies the state to which the hardware can automatically transition the VDD_MPU_L voltage domain."; 166 auto_ctrl_vdd_core_l 2 rw type(auto_ctrl_vdd_iva_l_status) "This bit field specifies the state to which the hardware can automatically transition the VDD_CORE_L voltage domain."; 167 }; 168 169 constants pwrreq_cond_status width(2) "" { 170 PWRREQ_COND_0 = 0 "is never de-asserted"; 171 PWRREQ_COND_1 = 1 "is de-asserted if all voltage domain are in SLEEP, RET or OFF state. Conversely, is asserted upon any voltage domain entering or staying in ON state."; 172 PWRREQ_COND_2 = 2 "is de-asserted if all voltage domain are in RET or OFF state. Conversely, is asserted upon any voltage domain entering or staying in ON or SLEEP state."; 173 PWRREQ_COND_3 = 3 "is de-asserted if all voltage domain are in OFF state. Conversely, is asserted upon any voltage domain entering or staying in ON or SLEEP or RET state."; 174 }; 175 176 register prm_pwrreqctrl addr(base, 0x14) "This register allows controlling the signal towards power IC." { 177 _ 30 mbz; 178 pwrreq_cond 2 rw type(pwrreq_cond_status) "Control upon which condition from MPU, IVA and CORE voltage domainsPWRREQ is de-asserted."; 179 }; 180 181 register prm_pscon_count addr(base, 0x18) "This register allows controlling 2 parameters for power state controller. [warm reset insensitive]" { 182 _ 16 mbz; 183 ponout_2_pgoodin_time 8 rw "The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS. The duration is computed as 8 x NbCycles of system clock cycles."; 184 pcharge_time 8 rw "Number of system clock cycles for the SRAM precharge duration."; 185 }; 186 187 register prm_io_count addr(base, 0x1C) "This register allows controlling LPDDR2 I/O isolation removal setup. [warm reset insensitive]" { 188 _ 24 mbz; 189 iso_2_on_time 8 rw "Determines the setup time of the LPDDR2 IOs going out of isolation. Counting on the system clock. Target is 1.5us."; 190 }; 191 192 constants global_wuen_status width(1) "" { 193 GLOBAL_WUEN_0 = 0 "All individual I/O WUEN are gated in the Spinner logic (overriden to 0)."; 194 GLOBAL_WUEN_1 = 1 "All individual I/O WUEN from control module are going to IOs."; 195 }; 196 197 constants wuclk_ctrl_status width(1) "" { 198 WUCLK_CTRL_0 = 0 "WUCLKIN signal is driven to 0. I/O wakeup daisy chain is functional as well as I/O whose wakeup feature is enabled."; 199 WUCLK_CTRL_1 = 1 "WUCLKIN signal is driven to 1. I/O wakeup daisy chain is reset and is latching current pad states and WUEN inputs."; 200 }; 201 202 constants ioon_status_status width(1) "" { 203 IOON_STATUS_0_r = 0 "Part or all of the IOs are not in the ON state, that is are in isolation state"; 204 IOON_STATUS_1_r = 1 "All IOs are in the ON state"; 205 }; 206 207 constants isoovr_extend_status width(1) "" { 208 ISOOVR_EXTEND_0 = 0 "Non-EMIF I/O isolation is not extended. 'EMIF_ON' I/O transition happens as soon as automatic restore is completed"; 209 ISOOVR_EXTEND_1 = 1 "Non-EMIF I/O isolation is extended. 'EMIF_ON' I/O transition is stalled"; 210 }; 211 212 constants isoclk_override_status width(1) "" { 213 ISOCLK_OVERRIDE_0 = 0 "ISOCLKIN signal is not overriden."; 214 ISOCLK_OVERRIDE_1 = 1 "ISOCLKIN signal is overriden to active value (1)."; 215 }; 216 217 register prm_io_pmctrl addr(base, 0x20) "This register allows overriding ISOCLK signal towards I/O pad ring." { 218 _ 15 mbz; 219 global_wuen 1 rw type(global_wuen_status) "Global I/O wakeup enable. This is a gating condition to all individual I/O WUEN coming from control module. Gating is done in the Spinner logic."; 220 _ 6 mbz; 221 wuclk_status 1 ro "Gives value of WUCLKOUT signal coming back from I/O pad ring."; 222 wuclk_ctrl 1 rw type(wuclk_ctrl_status) "Direct control on WUCLKIN signal to I/O pad ring."; 223 _ 2 mbz; 224 ioon_status 1 ro type(ioon_status_status) "Gives the functional status of the I/O ring."; 225 isoovr_extend 1 rw type(isoovr_extend_status) "Control non-EMIF I/O isolation extension upon a device wakeup from OFF mode."; 226 _ 2 mbz; 227 isoclk_status 1 ro "Gives value of ISOCLKOUT signal coming back from I/O pad ring."; 228 isoclk_override 1 rw type(isoclk_override_status) "Override control on ISOCLKIN signal to I/O pad ring. Override should be used at boot time only when it is needed to change the mode of an I/O from 1.8-V default mode to 1.2-V mode. When not overriden, this signal is controlled by hardware only."; 229 }; 230 231 constants stable_prescal_status width(2) "" { 232 STABLE_PRESCAL_0 = 0 "Ramp-up counter is incremented every 32 system clock cycles"; 233 STABLE_PRESCAL_1 = 1 "Ramp-up counter is incremented every 256 system clock cycles"; 234 STABLE_PRESCAL_2 = 2 "Ramp-up counter is incremented every 2048 system clock cycles"; 235 STABLE_PRESCAL_3 = 3 "Ramp-up counter is incremented every 16384 system clock cycles"; 236 }; 237 238 register prm_voltsetup_warmreset addr(base, 0x24) "This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions with OFF state. [warm reset insensitive]" { 239 _ 22 mbz; 240 stable_prescal 2 rw type(stable_prescal_status) "Determines prescaler for stabilization duration counting."; 241 _ 2 mbz; 242 stable_count 6 rw "Determines the stabilization duration of all VDD_xxx_L regulators upon a global warm reset assertion. The duration is computed according to Stable_Prescal."; 243 }; 244 245 register prm_voltsetup_core_off addr(base, 0x28) "This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions with OFF state. [warm reset insensitive]" { 246 _ 6 mbz; 247 ramp_down_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-down duration counting."; 248 _ 2 mbz; 249 ramp_down_count 6 rw "Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal."; 250 _ 6 mbz; 251 ramp_up_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-up duration counting."; 252 _ 2 mbz; 253 ramp_up_count 6 rw "Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_CORE_L will be at a valid ON voltage before SYS_NRESPWRON is de-asserted."; 254 }; 255 256 register prm_voltsetup_mpu_off addr(base, 0x2C) "This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MPU_L domain transitions to or from OFF state. [warm reset insensitive]" { 257 _ 6 mbz; 258 ramp_down_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-down duration counting."; 259 _ 2 mbz; 260 ramp_down_count 6 rw "Determines the ramp-down duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Down_Prescal."; 261 _ 6 mbz; 262 ramp_up_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-up duration counting."; 263 _ 2 mbz; 264 ramp_up_count 6 rw "Determines the ramp-up duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_MPU_L will be at a valid ON voltage before SYS_NRESPWRON is de-asserted."; 265 }; 266 267 register prm_voltsetup_iva_off addr(base, 0x30) "This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_IVA_L domain transitions to or from OFF state. [warm reset insensitive]" { 268 _ 6 mbz; 269 ramp_down_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-down duration counting."; 270 _ 2 mbz; 271 ramp_down_count 6 rw "Determines the ramp-down duration of VDD_IVA_L regulators. The duration is computed according to Ramp_Down_Prescal."; 272 _ 6 mbz; 273 ramp_up_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-up duration counting."; 274 _ 2 mbz; 275 ramp_up_count 6 rw "Determines the ramp-up duration of VDD_IVA_L regulators. The duration is computed according to Ramp_Up_Prescal. At cold reset, PRCM assumes that VDD_IVA_L will be at a valid ON voltage before SYS_NRESPWRON is de-asserted."; 276 }; 277 278 register prm_voltsetup_core_ret_sleep addr(base, 0x34) "This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_CORE_L domain transitions between ON and RET or SLEEP state. [warm reset insensitive]" { 279 _ 6 mbz; 280 ramp_down_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-down duration counting."; 281 _ 2 mbz; 282 ramp_down_count 6 rw "Determines the ramp-down duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Down_Prescal."; 283 _ 6 mbz; 284 ramp_up_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-up duration counting."; 285 _ 2 mbz; 286 ramp_up_count 6 rw "Determines the ramp-up duration of VDD_CORE_L regulators. The duration is computed according to Ramp_Up_Prescal."; 287 }; 288 289 register prm_voltsetup_mpu_ret_sleep addr(base, 0x38) "This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_MPU_L domain transitions between ON and RET or SLEEP state. [warm reset insensitive]" { 290 _ 6 mbz; 291 ramp_down_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-down duration counting."; 292 _ 2 mbz; 293 ramp_down_count 6 rw "Determines the ramp-down duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Down_Prescal."; 294 _ 6 mbz; 295 ramp_up_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-up duration counting."; 296 _ 2 mbz; 297 ramp_up_count 6 rw "Determines the ramp-up duration of VDD_MPU_L regulators. The duration is computed according to Ramp_Up_Prescal."; 298 }; 299 300 register prm_voltsetup_iva_ret_sleep addr(base, 0x3C) "This register provides bit fields for specifying voltage ramp-up and ramp-down times for PRM managed external regulators. These values are used for VDD_IVA_L domain transitions between ON and RET or SLEEP state. [warm reset insensitive]" { 301 _ 6 mbz; 302 ramp_down_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-down duration counting."; 303 _ 2 mbz; 304 ramp_down_count 6 rw "Determines the ramp-down duration of VDD_IVA_L regulators. The duration is computed according to Ramp_Down_Prescal."; 305 _ 6 mbz; 306 ramp_up_prescal 2 rw type(stable_prescal_status) "Determines prescaler for ramp-up duration counting."; 307 _ 2 mbz; 308 ramp_up_count 6 rw "Determines the ramp-up duration of VDD_IVA_L regulators. The duration is computed according to Ramp_Up_Prescal."; 309 }; 310 311 constants timeouten_status width(1) "" { 312 TIMEOUTEN_0 = 0 "Timeout is disabled. Loop will wait indefinitely."; 313 TIMEOUTEN_1 = 1 "Timeout will occur when TIMEOUT cycles have elapsed."; 314 }; 315 316 constants initvdd_status width(1) "" { 317 INITVDD_0 = 0 "Reset the initialization bit."; 318 INITVDD_1 = 1 "The positive edge of InitVdd triggers a write of the value in the InitVoltage into the Voltage Processor."; 319 }; 320 321 constants forceupdate_status width(1) "" { 322 FORCEUPDATE_0 = 0 "Reset the force bit."; 323 FORCEUPDATE_1 = 1 "The positive edge of ForceUpdate triggers an update of the voltage to the SMPS."; 324 }; 325 326 constants vpenable_status width(1) "" { 327 VPENABLE_0 = 0 "Disables the Voltage Processor."; 328 VPENABLE_1 = 1 "Enables the Voltage Processor."; 329 }; 330 331 register prm_vp_core_config addr(base, 0x40) "This register allows the configuration of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)." { 332 erroroffset 8 rw "Offset value in the Error to Voltage converter (two's complement number)."; 333 errorgain 8 rw "Gain value in the Error to Voltage converter (two's complement number)."; 334 initvoltage 8 rw "Set the initial voltage level of the SMPS. It must be reconfigured before enable the SmartReflex around a new OPP."; 335 _ 4 mbz; 336 timeouten 1 rw type(timeouten_status) "Enable or disable the timeout capability of the Voltage Controller State Machine."; 337 initvdd 1 rw type(initvdd_status) "Initializes the voltage in the Voltage Processor."; 338 forceupdate 1 rw type(forceupdate_status) "Forces an update of the SMPS."; 339 vpenable 1 rw type(vpenable_status) "Enables or disables the Voltage Processor updates on SR_SInterruptz."; 340 }; 341 342 constants vpinidle_status width(1) "" { 343 VPINIDLE_0_r = 0 "The Voltage Processor for CORE is processing. Warm reset sensitive"; 344 VPINIDLE_1_r = 1 "The Voltage Processor for CORE is in idle state."; 345 }; 346 347 register prm_vp_core_status addr(base, 0x44) "This register reflects the idle state of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L. This register is read only and automatically updated." { 348 _ 31 mbz; 349 vpinidle 1 ro type(vpinidle_status) "CORE Voltage Processor idle status."; 350 }; 351 352 register prm_vp_core_vlimitto addr(base, 0x48) "This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)." { 353 vddmax 8 rw "Defines the maximum voltage supply level."; 354 vddmin 8 rw "Defines the minimum voltage supply level."; 355 timeout 16 rw "Defines Voltage Controller maximum wait time for responses, measured in sysclk cycles."; 356 }; 357 358 register prm_vp_core_voltage addr(base, 0x4C) "This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)." { 359 forceupdatewait 24 rw "The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation."; 360 vpvoltage 8 ro "Indicates the current SMPS programmed voltage."; 361 }; 362 363 register prm_vp_core_vstepmax addr(base, 0x50) "This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to CORE Voltage Domain (VDD_CORE_L)." { 364 _ 8 mbz; 365 smpsoftwareaittimemax 16 rw "Slew rate for positive voltage step (in number of cycles per step)."; 366 vstepmax 8 rw "Maximum voltage step"; 367 }; 368 369 register prm_vp_core_vstepmin addr(base, 0x54) "This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the CORE Voltage Domain (VDD_CORE_L)." { 370 _ 8 mbz; 371 smpsoftwareaittimemin 16 rw "Slew rate for negative voltage step (in number of cycles per step)."; 372 vstepmin 8 rw "Minimum voltage step"; 373 }; 374 375 register prm_vp_mpu_config addr(base, 0x58) "This register allows the configuration of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)." { 376 erroroffset 8 rw "Offset value in the Error to Voltage converter (two's complement number)."; 377 errorgain 8 rw "Gain value in the Error to Voltage converter (two's complement number)."; 378 initvoltage 8 rw "Set the initial voltage level of the SMPS. It must be reconfigured before enable the SmartReflex around a new OPP."; 379 _ 4 mbz; 380 timeouten 1 rw type(timeouten_status) "Enable or disable the timeout capability of the Voltage Controller State Machine."; 381 initvdd 1 rw type(initvdd_status) "Initializes the voltage in the Voltage Processor."; 382 forceupdate 1 rw type(forceupdate_status) "Forces an update of the SMPS."; 383 vpenable 1 rw type(vpenable_status) "Enables or disables the Voltage Processor updates on SR_SInterruptz."; 384 }; 385 386 constants vpinidle_status1 width(1) "" { 387 VPINIDLE_0_r_1 = 0 "The Voltage Processor 1 is processing."; 388 VPINIDLE_1_r_1 = 1 "The Voltage Processor 1 is in idle state."; 389 }; 390 391 register prm_vp_mpu_status addr(base, 0x5C) "This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L. This register is read only and automatically updated." { 392 _ 31 mbz; 393 vpinidle 1 ro type(vpinidle_status1) "Voltage Processor 1 idle status."; 394 }; 395 396 register prm_vp_mpu_vlimitto addr(base, 0x60) "This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)." { 397 vddmax 8 rw "Defines the maximum voltage supply level."; 398 vddmin 8 rw "Defines the minimum voltage supply level."; 399 timeout 16 rw "Defines Voltage Controller maximum wait time for responses, measured in sysclk cycles."; 400 }; 401 402 register prm_vp_mpu_voltage addr(base, 0x64) "This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)." { 403 forceupdatewait 24 rw "The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation."; 404 vpvoltage 8 ro "Indicates the current SMPS programmed voltage."; 405 }; 406 407 register prm_vp_mpu_vstepmax addr(base, 0x68) "This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to MPU Voltage Domain (VDD_MPU_L)." { 408 _ 8 mbz; 409 smpsoftwareaittimemax 16 rw "Slew rate for positive voltage step (in number of cycles per step)."; 410 vstepmax 8 rw "Maximum voltage step"; 411 }; 412 413 register prm_vp_mpu_vstepmin addr(base, 0x6C) "This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_MPU_L)." { 414 _ 8 mbz; 415 smpsoftwareaittimemin 16 rw "Slew rate for negative voltage step (in number of cycles per step)."; 416 vstepmin 8 rw "Minimum voltage step"; 417 }; 418 419 register prm_vp_iva_config addr(base, 0x70) "This register allows the configuration of the Voltage Processor dedicated to IVAVoltage Domain (VDD_IVA_L)." { 420 erroroffset 8 rw "Offset value in the Error to Voltage converter (two's complement number)."; 421 errorgain 8 rw "Gain value in the Error to Voltage converter (two's complement number)."; 422 initvoltage 8 rw "Set the initial voltage level of the SMPS. It must be reconfigured before enable the SmartReflex around a new OPP."; 423 _ 4 mbz; 424 timeouten 1 rw type(timeouten_status) "Enable or disable the timeout capability of the Voltage Controller State Machine."; 425 initvdd 1 rw type(initvdd_status) "Initializes the voltage in the Voltage Processor."; 426 forceupdate 1 rw type(forceupdate_status) "Forces an update of the SMPS."; 427 vpenable 1 rw type(vpenable_status) "Enables or disables the Voltage Processor updates on SR_SInterruptz."; 428 }; 429 430 register prm_vp_iva_status addr(base, 0x74) "This register reflects the idle state of the Voltage Processor dedicated to the MPU Voltage Domain (VDD_IVA_L. This register is read only and automatically updated." { 431 _ 31 mbz; 432 vpinidle 1 ro type(vpinidle_status1) "Voltage Processor 1 idle status."; 433 }; 434 435 register prm_vp_iva_vlimitto addr(base, 0x78) "This register allows the configuration of the voltage limits and timeout values of the Voltage Processor dedicated to the IVA Voltage Domain (VDD_IVA_L)." { 436 vddmax 8 rw "Defines the maximum voltage supply level."; 437 vddmin 8 rw "Defines the minimum voltage supply level."; 438 timeout 16 rw "Defines Voltage Controller maximum wait time for responses, measured in sysclk cycles."; 439 }; 440 441 register prm_vp_iva_voltage addr(base, 0x7C) "This register indicates the current value of the SMPS voltage for the Voltage Processor dedicated to the IVA Voltage Domain (VDD_IVA_L)." { 442 forceupdatewait 24 rw "The time voltage processor needs to wait for SMPS to be settled after receiving SMPS acknowledge. This wait only be used during force_update operation."; 443 vpvoltage 8 ro "Indicates the current SMPS programmed voltage."; 444 }; 445 446 register prm_vp_iva_vstepmax addr(base, 0x80) "This register allows the programming of the maximum voltage step and waiting time of the Voltage Processor dedicated to IVA Voltage Domain (VDD_IVA_L)." { 447 _ 8 mbz; 448 smpsoftwareaittimemax 16 rw "Slew rate for positive voltage step (in number of cycles per step)."; 449 vstepmax 8 rw "Maximum voltage step"; 450 }; 451 452 register prm_vp_iva_vstepmin addr(base, 0x84) "This register allows the programming of the minimum voltage step and waiting time of the Voltage Processor dedicated to the IVA Voltage Domain (VDD_IVA_L)." { 453 _ 8 mbz; 454 smpsoftwareaittimemin 16 rw "Slew rate for negative voltage step (in number of cycles per step)."; 455 vstepmin 8 rw "Minimum voltage step"; 456 }; 457 458 register prm_vc_smps_sa addr(base, 0x88) "This register allows the setting of the I2C slave address of the Power IC device. [warm reset insensitive]" { 459 _ 9 mbz; 460 sa_vdd_mpu_l 7 rw "Set the I2C slave address value for the third (if any) Power IC device."; 461 _ 1 mbz; 462 sa_vdd_iva_l 7 rw "Set the I2C slave address value for the second (if any) Power IC device."; 463 _ 1 mbz; 464 sa_vdd_core_l 7 rw "Set the I2C slave address value for the first Power IC device."; 465 }; 466 467 register prm_vc_val_smps_ra_vol addr(base, 0x8C) "This register allows the setting of the voltage configuration register address for the VDD channels. [warm reset insensitive]" { 468 _ 8 mbz; 469 volra_vdd_mpu_l 8 rw "Voltage configuration register address value for VDD_MPU_L channel"; 470 volra_vdd_iva_l 8 rw "Voltage configuration register address value for VDD_IVA_L channel (if VDD_IVA_L source is placed in same chip as VDD_MPU_L source and have different voltage configuration register)"; 471 volra_vdd_core_l 8 rw "Voltage configuration register address value for the VDD_CORE_L channel (if VDD_CORE_L source is placed in same chip as VDD_MPU_L source and has different voltage configuration register)"; 472 }; 473 474 register prm_vc_val_smps_ra_cmd addr(base, 0x90) "Command (ON/ON-Low-Power/Retention/OFF) configuration register address values for the VDD channels (if used SMPS chips have different command configuration register than voltage configuration register) [warm reset insensitive]" { 475 _ 8 mbz; 476 cmdra_vdd_mpu_l 8 rw "Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_MPU_L channel"; 477 cmdra_vdd_iva_l 8 rw "Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_IVA_L channel (if VDD_IVA_L source has different command configuration register than voltage VDD_MPU_L)"; 478 cmdra_vdd_core_l 8 rw "Command (ON/ON-Low-Power /Retention/OFF) configuration register address value for VDD_CORE_L channel (if VDD_CORE_L source has different command configuration register than voltage VDD_MPU_L)"; 479 }; 480 481 register prm_vc_val_cmd_vdd_core_l addr(base, 0x94) "This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_CORE_L channel. [warm reset insensitive]" { 482 on 8 rw "Set the ON command value."; 483 onlp 8 rw "Set the ON-Low-Power command value."; 484 ret 8 rw "Set the RET command value."; 485 off 8 rw "Set the OFF command value."; 486 }; 487 488 register prm_vc_val_cmd_vdd_mpu_l addr(base, 0x98) "This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_MPU_L channel. [warm reset insensitive]" { 489 on 8 rw "Set the ON command value."; 490 onlp 8 rw "Set the ON-Low-Power command value."; 491 ret 8 rw "Set the RET command value."; 492 off 8 rw "Set the OFF command value."; 493 }; 494 495 register prm_vc_val_cmd_vdd_iva_l addr(base, 0x9C) "This register allows the setting of the ON/ON-Low-Power/Retention/OFF command values for VDD_IVA_L channel. [warm reset insensitive]" { 496 on 8 rw "Set the ON command value."; 497 onlp 8 rw "Set the ON-Low-Power command value."; 498 ret 8 rw "Set the RET command value."; 499 off 8 rw "Set the OFF command value."; 500 }; 501 502 constants valid_status width(1) "" { 503 VALID_0_r = 0 "The last command send has been acknowledged"; 504 VALID_1 = 1 "Pending command is being process"; 505 }; 506 507 register prm_vc_val_bypass addr(base, 0xA0) "Bypass data values register used for bypass command channel to send other configuration information (other then voltage configuration parameters) for SMPS chips which have no other configuration interface then this I2C interface. [warm reset insensitive]" { 508 _ 7 mbz; 509 valid 1 rw type(valid_status) "This bit validates the bypass command. It is automatically cleared by hardware either after getting the acknowledge back from the SMPS or if an error occured."; 510 data 8 rw "Data to send to the Power IC device."; 511 regaddr 8 rw "Set the address of Power IC device register to configure."; 512 _ 1 mbz; 513 slaveaddr 7 rw "Set the I2C slave address value."; 514 }; 515 516 constants racen_vdd_mpu_l_status width(1) "" { 517 RACEN_VDD_MPU_L_0 = 0 "VDD_MPU_L channel uses VOLRA values for register address of VFSM-s commands. VFSM-s commands goes also to voltage configuration register."; 518 RACEN_VDD_MPU_L_1 = 1 "VDD_MPU_L channel uses CMDRA values for register address of VFSM-s commands. VFSM-s commands goes to different command configuration register."; 519 }; 520 521 constants rac_vdd_mpu_l_status width(1) "" { 522 RAC_VDD_MPU_L_0 = 0 "Select CMDRA_VDD_CORE_L for VDD_MPU_L channel"; 523 RAC_VDD_MPU_L_1 = 1 "Select CMDRA_VDD_MPU_L for VDD_MPU_L channel"; 524 }; 525 526 constants rav_vdd_mpu_l_status width(1) "" { 527 RAV_VDD_MPU_L_0 = 0 "Select VOLRA_VDD_CORE_L for VDD_MPU_L channel"; 528 RAV_VDD_MPU_L_1 = 1 "Select VOLRA_VDD_MPU_L for VDD_MPU_L channel"; 529 }; 530 531 constants cmd_vdd_mpu_l_status width(1) "" { 532 CMD_VDD_MPU_L_0 = 0 "VDD_MPU_L channel use VC_VAL_CMD_VDD_CORE_L set for command values"; 533 CMD_VDD_MPU_L_1 = 1 "VDD_MPU_L channel use VC_VAL_CMD_VDD_MPU_L set for command values"; 534 }; 535 536 constants sa_vdd_mpu_l_status width(1) "" { 537 SA_VDD_MPU_L_0 = 0 "Select SA_VDD_CORE_L for VDD_MPU_L channel"; 538 SA_VDD_MPU_L_1 = 1 "Select SA_VDD_MPU_L for VDD_MPU_L channel"; 539 }; 540 541 constants cmd_vdd_iva_l_status width(1) "" { 542 CMD_VDD_IVA_L_0 = 0 "VDD_IVA_L channel use VC_VAL_CMD_VDD_MPU_L set for command values"; 543 CMD_VDD_IVA_L_1 = 1 "VDD_IVA_L channel use VC_VAL_CMD_VDD_IVA_L set for command values"; 544 }; 545 546 constants racen_vdd_iva_l_status width(1) "" { 547 RACEN_VDD_IVA_L_0 = 0 "VDD_IVA_L channel uses VOLRA values for register address of VFSM-s commands. VFSM-s commands goes also to voltage configuration register."; 548 RACEN_VDD_IVA_L_1 = 1 "VDD_IVA_L channel uses CMDRA values for register address of VFSM-s commands. VFSM-s commands goes to different command configuration register."; 549 }; 550 551 constants rac_vdd_iva_l_status width(1) "" { 552 RAC_VDD_IVA_L_0 = 0 "Select CMDRA_VDD_MPU_L for VDD_IVA_L channel"; 553 RAC_VDD_IVA_L_1 = 1 "Select CMDRA_VDD_IVA_L for VDD_IVA_L channel"; 554 }; 555 556 constants rav_vdd_iva_l_status width(1) "" { 557 RAV_VDD_IVA_L_0 = 0 "Select VOLRA_VDD_MPU_L for VDD_IVA_L channel"; 558 RAV_VDD_IVA_L_1 = 1 "Select VOLRA_VDD_IVA_L for VDD_IVA_L channel"; 559 }; 560 561 constants sa_vdd_iva_l_status width(1) "" { 562 SA_VDD_IVA_L_0 = 0 "Select SA_VDD_MPU_L for VDD_IVA_L channel"; 563 SA_VDD_IVA_L_1 = 1 "Select SA_VDD_IVA_L for VDD_IVA_L channel"; 564 }; 565 566 constants racen_vdd_core_l_status width(1) "" { 567 RACEN_VDD_CORE_L_0 = 0 "VDD_CORE_L channel use VOLRA values for register address of VFSM-s commands. VFSM-s commands goes also to voltage configuration register."; 568 RACEN_VDD_CORE_L_1 = 1 "VDD_CORE_L channel use CMDRA values for register address of VFSM-s commands. VFSM-s commands goes to different command configuration register."; 569 }; 570 571 constants rac_vdd_core_l_status width(1) "" { 572 RAC_VDD_CORE_L_0 = 0 "Select CMDRA_VDD_MPU_L for the VDD_CORE_L channel."; 573 RAC_VDD_CORE_L_1 = 1 "Select CMDRA_VDD_CORE_L for the VDD_CORE_L channel."; 574 }; 575 576 constants rav_vdd_core_l_status width(1) "" { 577 RAV_VDD_CORE_L_0 = 0 "Select VOLRA_VDD_MPU_L for the VDD_CORE_L channel."; 578 RAV_VDD_CORE_L_1 = 1 "Select VOLRA_VDD_CORE_L for the VDD_CORE_L channel."; 579 }; 580 581 constants sa_vdd_core_l_status width(1) "" { 582 SA_VDD_CORE_L_0 = 0 "Select SA_VDD_MPU_L for the VDD_CORE_L channel."; 583 SA_VDD_CORE_L_1 = 1 "Select SA_VDD_CORE_L for the VDD_CORE_L channel."; 584 }; 585 586 register prm_vc_cfg_channel addr(base, 0xA4) "This register allows the configuration pointers for both VDD channels. [warm reset insensitive]" { 587 _ 11 mbz; 588 racen_vdd_mpu_l 1 rw type(racen_vdd_mpu_l_status) "Enable bit for usage of RAC_VDD_MPU_L"; 589 rac_vdd_mpu_l 1 rw type(rac_vdd_mpu_l_status) "Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_MPU_L channel. (This bit has no influence on the VDD_MPU_L channel.)"; 590 rav_vdd_mpu_l 1 rw type(rav_vdd_mpu_l_status) "Voltage configuration register address pointer for VDD_MPU_L channel. (This bit has no influence on the VDD_MPU_L channel.)"; 591 cmd_vdd_mpu_l 1 rw type(cmd_vdd_mpu_l_status) "Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_MPU_L channel. (This bit has no influence on the VDD_MPU_L channel.)"; 592 sa_vdd_mpu_l 1 rw type(sa_vdd_mpu_l_status) "Slave address pointer for VDD_MPU_L channel. (This bit has no influence on the VDD_MPU_L channel.)"; 593 _ 3 mbz; 594 cmd_vdd_iva_l 1 rw type(cmd_vdd_iva_l_status) "Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_IVA_L channel"; 595 racen_vdd_iva_l 1 rw type(racen_vdd_iva_l_status) "Enable bit for usage of RAC_VDD_IVA_L"; 596 rac_vdd_iva_l 1 rw type(rac_vdd_iva_l_status) "Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_IVA_L channel"; 597 rav_vdd_iva_l 1 rw type(rav_vdd_iva_l_status) "Voltage configuration register address pointer for VDD_IVA_L channel."; 598 sa_vdd_iva_l 1 rw type(sa_vdd_iva_l_status) "Slave address pointer for VDD_IVA_L channel."; 599 _ 3 mbz; 600 cmd_vdd_core_l 1 rw "Command values (ON/ON-Low-Power/Retention/OFF voltage values) set selection for VDD_CORE_L channel"; 601 racen_vdd_core_l 1 rw type(racen_vdd_core_l_status) "Enable bit for usage of RAC_VDD_CORE_L."; 602 rac_vdd_core_l 1 rw type(rac_vdd_core_l_status) "Command (ON/ON-Low-Power/Retention/OFF) configuration register address pointer for VDD_CORE_L channel."; 603 rav_vdd_core_l 1 rw type(rav_vdd_core_l_status) "Voltage configuration register address pointer for VDD_CORE_L channel."; 604 sa_vdd_core_l 1 rw type(sa_vdd_core_l_status) "Slave address pointer for VDD_CORE_L channel."; 605 }; 606 607 constants dfilteren_status width(1) "" { 608 DFILTEREN_0 = 0 "I2C bus digital filter rejects all glitches smaller than 1 sytem clock cycle"; 609 DFILTEREN_1 = 1 "I2C bus digital filter rejects all glitches smaller than 2 sytem clock cycles"; 610 }; 611 612 constants hsmodeen_status width(1) "" { 613 HSMODEEN_0 = 0 "Disables the I2C high-speed mode"; 614 HSMODEEN_1 = 1 "Enables the I2C high-speed mode"; 615 }; 616 617 register prm_vc_cfg_i2c_mode addr(base, 0xA8) "I2C configuration register. [warm reset insensitive]" { 618 _ 25 mbz; 619 dfilteren 1 rw type(dfilteren_status) "This field enables double filter procedure for IC input lines"; 620 _ 1 mbz; 621 srmodeen 1 rw type(stable_prescal_status) "Enables the IC repeated start operation mode.(Effect of holding the SCL and SDA lines low, in effect blocking the I2C bus from losing arbitration between repeated start points). . Use of this feature results from a trade-off between speed and power consumption of I2C interface. ."; 622 hsmodeen 1 rw type(hsmodeen_status) "Enables IC bus high-speed mode."; 623 hsmcode 3 rw "Master code value for IC high-speed preamble transmission."; 624 }; 625 626 register prm_vc_cfg_i2c_clk addr(base, 0xAC) "I2C Interface clock configuration parameters. [warm reset insensitive]" { 627 hsscll 8 rw "Number of the system clock cycles, necessary to count the low period of the I2C clock signal, when the I2C interface runs in high-speed mode of operation. The value of the bit field is automatically increased by 7."; 628 hssclh 8 rw "Number of the system clock cycles, necessary to count the high period of the I2C clock signal, when the I2C interface runs in high-speed mode of operation. The value of the bit field is automatically increased by 5."; 629 scll 8 rw "Number of the system clock cycles, necessary to count the low period of the I2C clock signal, when the I2C interface runs in fast mode of operation. The value of the bit field is automatically increased by 7."; 630 sclh 8 rw "Number of the system clock cycles, necessary to count the high period of the I2C clock signal, when the I2C interface runs in fast mode of operation. The value of the bit field is automatically increased by 5."; 631 }; 632 633 register prm_sram_count addr(base, 0xB0) "Common setup for SRAM LDO transition counters. Applies to all voltage domains. [warm reset insensitive]" { 634 startup_count 8 rw "Determines the start-up duration of SRAM and ABB LDO. The duration is computed as 16 x NbCycles of system clock cycles. Target is 50us."; 635 slpcnt_value 8 rw "Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high. Counting on system clock. Target is 2us."; 636 vsetupcnt_value 8 rw "SRAM LDO rampup time from retention to active mode. The duration is computed as 8 x NbCycles of system clock cycles. Target is 30us."; 637 _ 2 mbz; 638 pchargecnt_value 6 rw "Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good. Counting on system clock. Target is 600ns."; 639 }; 640 641 constants disable_rta_export_status width(1) "" { 642 DISABLE_RTA_EXPORT_0 = 0 "HD memory RTA feature is enabled"; 643 DISABLE_RTA_EXPORT_1 = 1 "HD memory RTA feature is disabled"; 644 }; 645 646 register prm_sram_wkup_setup addr(base, 0xB4) "Setup of memory in WKUP voltage domain. [warm reset insensitive]" { 647 _ 31 mbz; 648 disable_rta_export 1 rw type(disable_rta_export_status) "Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 649 }; 650 651 constants aipoff_status width(1) "" { 652 AIPOFF_0 = 0 "AIPOFF signal is not overriden"; 653 AIPOFF_1 = 1 "AIPOFF signal is overriden to 1. Corresponding SRAM LDO is disabled and in HZ mode."; 654 }; 655 656 constants enfunc4_status width(1) "" { 657 ENFUNC4_0 = 0 "One external clock is supplied"; 658 ENFUNC4_1 = 1 "No external clock is supplied"; 659 }; 660 661 constants enfunc3_export_status width(1) "" { 662 ENFUNC3_EXPORT_0 = 0 "Sub regulation is disabled"; 663 ENFUNC3_EXPORT_1 = 1 "Sub regulation is enabled"; 664 }; 665 666 constants enfunc2_export_status width(1) "" { 667 ENFUNC2_EXPORT_0 = 0 "External cap is used"; 668 ENFUNC2_EXPORT_1 = 1 "External cap is not used"; 669 }; 670 671 constants enfunc1_export_status width(1) "" { 672 ENFUNC1_EXPORT_0 = 0 "Short circuit protection is disabled"; 673 ENFUNC1_EXPORT_1 = 1 "Short circuit protection is enabled"; 674 }; 675 676 constants abboff_sleep_export_status width(1) "" { 677 ABBOFF_SLEEP_EXPORT_0 = 0 "SRAMNWA supplied with VDDS"; 678 ABBOFF_SLEEP_EXPORT_1 = 1 "SRAMNWA supplied with VDDAR"; 679 }; 680 681 register prm_ldo_sram_core_setup addr(base, 0xB8) "Setup of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" { 682 _ 23 mbz; 683 aipoff 1 rw type(aipoff_status) "Override on AIPOFF input of SRAM LDO."; 684 enfunc5 1 rw type(stable_prescal_status) "ENFUNC5 input of SRAM LDO."; 685 enfunc4 1 rw type(enfunc4_status) "ENFUNC4 input of SRAM LDO."; 686 enfunc3_export 1 rw type(enfunc3_export_status) "ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 687 enfunc2_export 1 rw type(enfunc2_export_status) "ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 688 enfunc1_export 1 rw type(enfunc1_export_status) "ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 689 abboff_sleep_export 1 rw type(abboff_sleep_export_status) "Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 690 abboff_act_export 1 rw type(abboff_sleep_export_status) "Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 691 disable_rta_export 1 rw type(disable_rta_export_status) "Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 692 }; 693 694 constants sram_in_transition_status width(1) "" { 695 SRAM_IN_TRANSITION_0_r = 0 "SRAM LDO state machine is stable"; 696 SRAM_IN_TRANSITION_1_r = 1 "SRAM LDO state machine is in transition state"; 697 }; 698 699 constants sramldo_status_status width(1) "" { 700 SRAMLDO_STATUS_0_r = 0 "SRAMLDO is in ACTIVE mode."; 701 SRAMLDO_STATUS_1_r = 1 "SRAMLDO is on RETENTION mode."; 702 }; 703 704 constants retmode_enable_status width(1) "" { 705 RETMODE_ENABLE_0 = 0 "SRAM LDO is not allowed to go to RET mode"; 706 RETMODE_ENABLE_1 = 1 "SRAM LDO go to RET mode when all memory of voltage domain are OFF or RET"; 707 }; 708 709 register prm_ldo_sram_core_ctrl addr(base, 0xBC) "Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" { 710 _ 22 mbz; 711 sram_in_transition 1 ro type(sram_in_transition_status) "Status indicating SRAM LDO state machine state."; 712 sramldo_status 1 ro type(sramldo_status_status) "SRAMLDO status"; 713 _ 7 mbz; 714 retmode_enable 1 rw type(retmode_enable_status) "Control if the SRAM LDO retention mode is used or not."; 715 }; 716 717 register prm_ldo_sram_mpu_setup addr(base, 0xC0) "Setup of the SRAM LDO for MPU voltage domain. [warm reset insensitive]" { 718 _ 23 mbz; 719 aipoff 1 rw type(aipoff_status) "Override on AIPOFF input of SRAM LDO."; 720 enfunc5 1 rw type(stable_prescal_status) "ENFUNC5 input of SRAM LDO."; 721 enfunc4 1 rw type(enfunc4_status) "ENFUNC4 input of SRAM LDO."; 722 enfunc3_export 1 rw type(enfunc3_export_status) "ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 723 enfunc2_export 1 rw type(enfunc2_export_status) "ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 724 enfunc1_export 1 rw type(enfunc1_export_status) "ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 725 abboff_sleep_export 1 rw type(abboff_sleep_export_status) "Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 726 abboff_act_export 1 rw type(abboff_sleep_export_status) "Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 727 disable_rta_export 1 rw type(disable_rta_export_status) "Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 728 }; 729 730 register prm_ldo_sram_mpu_ctrl addr(base, 0xC4) "Control and status of the SRAM LDO for MPU voltage domain. [warm reset insensitive]" { 731 _ 22 mbz; 732 sram_in_transition 1 ro type(sram_in_transition_status) "Status indicating SRAM LDO state machine state."; 733 sramldo_status 1 ro type(sramldo_status_status) "SRAMLDO status"; 734 _ 7 mbz; 735 retmode_enable 1 rw type(retmode_enable_status) "Control if the SRAM LDO retention mode is used or not."; 736 }; 737 738 register prm_ldo_sram_iva_setup addr(base, 0xC8) "Setup of the SRAM LDO for IVA voltage domain. [warm reset insensitive]" { 739 _ 23 mbz; 740 aipoff 1 rw type(aipoff_status) "Override on AIPOFF input of SRAM LDO."; 741 enfunc5 1 rw type(stable_prescal_status) "ENFUNC5 input of SRAM LDO."; 742 enfunc4 1 rw type(enfunc4_status) "ENFUNC4 input of SRAM LDO."; 743 enfunc3_export 1 rw type(enfunc3_export_status) "ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 744 enfunc2_export 1 rw type(enfunc2_export_status) "ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 745 enfunc1_export 1 rw type(enfunc1_export_status) "ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 746 abboff_sleep_export 1 rw type(abboff_sleep_export_status) "Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 747 abboff_act_export 1 rw type(abboff_sleep_export_status) "Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 748 disable_rta_export 1 rw type(disable_rta_export_status) "Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bit field is automatically loaded with an Efuse value from control module. Bit field remains writable after this."; 749 }; 750 751 register prm_ldo_sram_iva_ctrl addr(base, 0xCC) "Control and status of the SRAM LDO for IVA voltage domain. [warm reset insensitive]" { 752 _ 22 mbz; 753 sram_in_transition 1 ro type(sram_in_transition_status) "Status indicating SRAM LDO state machine state."; 754 sramldo_status 1 ro type(sramldo_status_status) "SRAMLDO status"; 755 _ 7 mbz; 756 retmode_enable 1 rw type(retmode_enable_status) "Control if the SRAM LDO retention mode is used or not."; 757 }; 758 759 constants active_fbb_sel_status width(1) "" { 760 ACTIVE_FBB_SEL_0 = 0 "ABB LDO is in bypass mode"; 761 ACTIVE_FBB_SEL_1 = 1 "ABB LDO is in ABB Set1 mode"; 762 }; 763 764 constants active_rbb_sel_status width(1) "" { 765 ACTIVE_RBB_SEL_0 = 0 "ABB LDO is in bypass mode"; 766 ACTIVE_RBB_SEL_1 = 1 "ABB LDO is in ABB Set2 mode"; 767 }; 768 769 constants sr2en_status width(1) "" { 770 SR2EN_0 = 0 "ABB LDO is put in bypass mode"; 771 SR2EN_1 = 1 "ABB LDO will operate accordingly to settings"; 772 }; 773 774 register prm_ldo_abb_mpu_setup addr(base, 0xD0) "Selects the MPU_ABB LDO mode." { 775 _ 16 mbz; 776 sr2_wtcnt_value 8 rw "LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]"; 777 _ 4 mbz; 778 _ 1 mbz; 779 active_fbb_sel 1 rw type(active_fbb_sel_status) "Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive]"; 780 active_rbb_sel 1 rw type(active_rbb_sel_status) "Defines ABB LDO mode when MPU voltage is in OPP_TURBO. [warm reset insensitive]"; 781 sr2en 1 rw type(sr2en_status) "Enable ABB power management"; 782 }; 783 784 constants sr2_in_transition_status width(1) "" { 785 SR2_IN_TRANSITION_0_r = 0 ""; 786 SR2_IN_TRANSITION_1_r = 1 "Indicates that VBBLDO_CON is in transition and SR2_STATUS bits are not stable to read."; 787 }; 788 789 constants sr2_status_status width(2) "" { 790 SR2_STATUS_0_r = 0 "ABB LDO is placed in bypass mode."; 791 SR2_STATUS_1_r = 1 "ABB LDO is placed in ABB Set2 active mode"; 792 SR2_STATUS_2_r = 2 "ABB LDO is placed in ABB Set1 active mode."; 793 SR2_STATUS_3_r = 3 "Reserved"; 794 }; 795 796 constants opp_sel_status width(2) "" { 797 OPP_SEL_0 = 0 "default : Nominal"; 798 OPP_SEL_1 = 1 "Fast OPP"; 799 OPP_SEL_2 = 2 "Nominal"; 800 OPP_SEL_3 = 3 "Slow OPP"; 801 }; 802 803 register prm_ldo_abb_mpu_ctrl addr(base, 0xD4) "Control and Status of ABB on MPU voltage domain. [warm reset insensitive]" { 804 _ 25 mbz; 805 sr2_in_transition 1 ro type(sr2_in_transition_status) "Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion."; 806 _ 1 mbz; 807 sr2_status 2 ro type(sr2_status_status) "Indicate ABB LDO current operation status"; 808 opp_change 1 rw "When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL and ACTIVE_FBB_SEL/ACTIVE_RBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted."; 809 opp_sel 2 rw type(opp_sel_status) "Selects the OPP at which the MPU voltage domain is operating"; 810 }; 811 812 register prm_ldo_abb_iva_setup addr(base, 0xD8) "Selects the IVA_ABB LDO mode." { 813 _ 16 mbz; 814 sr2_wtcnt_value 8 rw "LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]"; 815 _ 4 mbz; 816 _ 1 mbz; 817 active_fbb_sel 1 rw type(active_fbb_sel_status) "Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive]"; 818 active_rbb_sel 1 rw type(active_rbb_sel_status) "Defines ABB LDO mode when IVA voltage is in OPP_TURBO. [warm reset insensitive]"; 819 sr2en 1 rw type(sr2en_status) "Enable ABB power management"; 820 }; 821 822 register prm_ldo_abb_iva_ctrl addr(base, 0xDC) "Control and Status of ABB on IVA voltage domain. [warm reset insensitive]" { 823 _ 25 mbz; 824 sr2_in_transition 1 ro type(sr2_in_transition_status) "Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion."; 825 _ 1 mbz; 826 sr2_status 2 ro type(sr2_status_status) "Indicate ABB LDO current operation status"; 827 opp_change 1 rw "When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL and ACTIVE_FBB_SEL/ACTIVE_RBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted."; 828 opp_sel 2 rw type(opp_sel_status) "Selects the OPP at which the IVA voltage domain is operating (Fast OPP, Nominal OPP or Slow OPP)"; 829 }; 830 831 register prm_ldo_bandgap_setup addr(base, 0xE0) "Control of the bandgap. [warm reset insensitive]" { 832 _ 24 mbz; 833 startup_count 8 rw "Determines the start-up duration of BANDGAP. The duration is computed as 32 x NbCycles of system clock cycles. Target is 100us."; 834 }; 835 836 constants emif2_offwkup_disable_status width(1) "" { 837 EMIF2_OFFWKUP_DISABLE_0 = 0 "Notifier is activated."; 838 EMIF2_OFFWKUP_DISABLE_1 = 1 "Notifier is not activated - stays low."; 839 }; 840 841 constants device_off_enable_status width(1) "" { 842 DEVICE_OFF_ENABLE_0 = 0 "Device is not allowed to perform transition to off mode"; 843 DEVICE_OFF_ENABLE_1 = 1 "Device is allowed to perform transition to off mode as soon as all power domains in MPU, IVA and CORE voltage are in OFF or OsoftwareRET state (open switch retention)"; 844 }; 845 846 register prm_device_off_ctrl addr(base, 0xE4) "This register is used to control device OFF transition." { 847 _ 22 mbz; 848 emif2_offwkup_disable 1 rw type(emif2_offwkup_disable_status) "Controls the EMIF2_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF2 upon a device wakeup from off mode. (Warm reset insensitive)"; 849 emif1_offwkup_disable 1 rw type(emif2_offwkup_disable_status) "Controls the EMIF1_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF1 upon a device wakeup from off mode. (Warm reset insensitive)"; 850 _ 7 mbz; 851 device_off_enable 1 rw type(device_off_enable_status) "Controls transition to device OFF mode."; 852 }; 853 854 register prm_phase1_cndp ro addr(base, 0xE8) "This register stores the start descriptor address of automatic restore phase1. [warm reset insensitive]" type(uint32); 855 856 register prm_phase2a_cndp ro addr(base, 0xEC) "This register stores the start descriptor address of automatic restore phase2A. [warm reset insensitive]" type(uint32); 857 858 register prm_phase2b_cndp ro addr(base, 0xF0) "This register stores the start descriptor address of automatic restore phase2B. [warm reset insensitive]" type(uint32); 859 860 constants byps_timeout_err_status width(1) "" { 861 BYPS_TIMEOUT_ERR_0 = 0 "No error"; 862 BYPS_TIMEOUT_ERR_1 = 1 "An error has been logged"; 863 }; 864 865 register prm_vc_errst addr(base, 0xF8) "This debug register logs the error status coming from Voltage Controller. Must be cleared by software." { 866 _ 5 mbz; 867 byps_timeout_err 1 rw1c type(byps_timeout_err_status) "Bypass command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost."; 868 byps_ra_err 1 rw1c type(byps_timeout_err_status) "Wrong register address error for bypass command"; 869 byps_sa_err 1 rw1c type(byps_timeout_err_status) "Wrong slave address error for bypass command"; 870 _ 2 mbz; 871 vfsm_timeout_err_mpu 1 rw1c type(byps_timeout_err_status) "MPU voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost."; 872 vfsm_ra_err_mpu 1 rw1c type(byps_timeout_err_status) "Wrong register address error for MPU voltage FSM"; 873 vfsm_sa_err_mpu 1 rw1c type(byps_timeout_err_status) "Wrong slave address error for MPU voltage FSM"; 874 smps_timeout_err_mpu 1 rw1c type(byps_timeout_err_status) "MPU voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost."; 875 smps_ra_err_mpu 1 rw1c type(byps_timeout_err_status) "Wrong register address error for MPU voltage processor"; 876 smps_sa_err_mpu 1 rw1c type(byps_timeout_err_status) "Wrong slave address error for MPU voltage processor"; 877 _ 2 mbz; 878 vfsm_timeout_err_iva 1 rw1c type(byps_timeout_err_status) "IVA voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost."; 879 vfsm_ra_err_iva 1 rw1c type(byps_timeout_err_status) "Wrong register address error for IVA voltage FSM"; 880 vfsm_sa_err_iva 1 rw1c type(byps_timeout_err_status) "Wrong slave address error for IVA voltage FSM"; 881 smps_timeout_err_iva 1 rw1c type(byps_timeout_err_status) "IVA voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost."; 882 smps_ra_err_iva 1 rw1c type(byps_timeout_err_status) "Wrong register address error for IVA voltage processor"; 883 smps_sa_err_iva 1 rw1c type(byps_timeout_err_status) "Wrong slave address error for IVA voltage processor"; 884 _ 2 mbz; 885 vfsm_timeout_err_core 1 rw1c type(byps_timeout_err_status) "CORE voltage FSM command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost."; 886 vfsm_ra_err_core 1 rw1c type(byps_timeout_err_status) "Wrong register address error for CORE voltage FSM"; 887 vfsm_sa_err_core 1 rw1c type(byps_timeout_err_status) "Wrong slave address error for CORE voltage FSM"; 888 smps_timeout_err_core 1 rw1c type(byps_timeout_err_status) "CORE voltage processor command frame is finished but is not acknowledged by the slave, or (I2C multimaster) arbitration lost."; 889 smps_ra_err_core 1 rw1c type(byps_timeout_err_status) "Wrong register address error for CORE voltage processor"; 890 smps_sa_err_core 1 rw1c type(byps_timeout_err_status) "Wrong slave address error for CORE voltage processor"; 891 }; 892};