1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_dct_l3interconnect.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_dct_l3interconnect msbfirst ( addr base ) "" { 29 30 31 register dct_version ro addr(base, 0x0) "IP Revision" type(uint32); 32 33 register dct_ctrl addr(base, 0x4) "DCT control register" { 34 _ 16 mbz; 35 busy 1 ro "IDCT/busy status 0: Idle 1: Busy"; 36 _ 14 mbz; 37 en 1 wo "Write 1 whenDCT_CFG[4] TRIG_SRC = 0 to start module operation. Read returns 0."; 38 }; 39 40 register dct_cfg addr(base, 0x8) "DCT configuration register" { 41 _ 18 mbz; 42 nmcus 6 rw "Number of MCUs (for FMT = 0, 1) or blocks (for FMT = 2) 0 = 1 MCU or block 1 = 2 MCUs or blocks ... 63 = 64 MCUs or blocks"; 43 _ 2 mbz; 44 autogating 1 rw "Internal clock gating on interface and functional clocks 0: Clocks are free-running 1: Clocks are gated off in subblocks that are not required for operation."; 45 trig_src 1 rw "Trigger source 0: Memory mapper register 1: Hardware start signal"; 46 inten 1 rw "0: Interrupt disabled 1: Interrupt enabled"; 47 fmt 2 rw "Data format 0: YUV4:2:0 format 1: YUV4:2:2 format 2: Sequential blocks format 3: Reserved"; 48 mode 1 rw "0: DCT 1: IDCT"; 49 }; 50 51 register dct_sptr addr(base, 0xC) "Spatial-domain data pointer, byte address" { 52 _ 19 mbz; 53 addr 8 rw "Address in 256-bit words Intention is that software write a byte address into the register. Hardware ignores the lowest 5 bits and bits 12..5 specifies the 256-bit/word memory address.."; 54 _ 5 mbz; 55 }; 56 57 register dct_fptr addr(base, 0x10) "Frequency-domain data pointer, byte address" { 58 _ 18 mbz; 59 addr 10 rw "Address in 128-bit words. Intention is that software write a byte address into the register. Hardware ignores the lowest 4 bits and bits 13..4 specifies the 128-bit/word memory address."; 60 _ 4 mbz; 61 }; 62};