1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_cortexm3_wkup.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_cortexm3_wkup msbfirst ( addr base ) "" { 29 30 31 register cortexm3_ctrl_reg addr(base, 0x0) "The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." { 32 _ 15 mbz; 33 int_cortex_2 1 rw "Interrupt to ARM Cortex-M3 CPU2"; 34 _ 15 mbz; 35 int_cortex_1 1 rw "Interrupt to ARM Cortex-M3 CPU1"; 36 }; 37 38 constants standbymode_status width(2) "" { 39 STANDBYMODE_1 = 1 "No-standby mode"; 40 STANDBYMODE_2 = 2 "Smart-standby mode"; 41 STANDBYMODE_3 = 3 "Smart-standby wakeup mode - normal mode to be used"; 42 }; 43 44 register standby_core_sysconfig addr(base, 0x4) "Standby protocol" { 45 _ 30 mbz; 46 standbymode 2 rw type(standbymode_status) "0x0: Force-standby mode"; 47 }; 48 49 constants idlemode_status width(2) "" { 50 IDLEMODE_1 = 1 "No-idle mode"; 51 IDLEMODE_2 = 2 "Smart-idle mode"; 52 IDLEMODE_3 = 3 "Smart-idle wakeup mode - normal mode to be used"; 53 }; 54 55 register idle_core_sysconfig addr(base, 0x8) "Idle protocol" { 56 _ 30 mbz; 57 idlemode 2 rw type(idlemode_status) "0x0: Force-idle mode"; 58 }; 59 60 register wugen_mevt0 addr(base, 0xC) "This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." { 61 mirq31 1 rw "Interrupt Mask bit 31"; 62 _ 1 mbz; 63 mirq29 1 rw "Interrupt Mask bit 29"; 64 mirq28 1 rw "Interrupt Mask bit 28"; 65 mirq27 1 rw "Interrupt Mask bit 27"; 66 mirq26 1 rw "Interrupt Mask bit 26"; 67 mirq25 1 rw "Interrupt Mask bit 25"; 68 mirq24 1 rw "Interrupt Mask bit 24"; 69 mirq23 1 rw "Interrupt Mask bit 23"; 70 mirq22 1 rw "Interrupt Mask bit 22"; 71 mirq21 1 rw "Interrupt Mask bit 21"; 72 mirq20 1 rw "Interrupt Mask bit 20"; 73 mirq19 1 rw "Interrupt Mask bit 19"; 74 mirq18 1 rw "Interrupt Mask bit 18"; 75 mirq17 1 rw "Interrupt Mask bit 17"; 76 mirq16 1 rw "Interrupt Mask bit 16"; 77 mirq15 1 rw "Interrupt Mask bit 15"; 78 mirq14 1 rw "Interrupt Mask bit 14"; 79 mirq13 1 rw "Interrupt Mask bit 13"; 80 mirq12 1 rw "Interrupt Mask bit 12"; 81 mirq11 1 rw "Interrupt Mask bit 11"; 82 mirq10 1 rw "Interrupt Mask bit 10"; 83 mirq9 1 rw "Interrupt Mask bit 9"; 84 mirq8 1 rw "Interrupt Mask bit 8"; 85 mirq7 1 rw "Interrupt Mask bit 7"; 86 _ 7 mbz; 87 }; 88 89 register wugen_mevt1 addr(base, 0x10) "This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." { 90 mirq63 1 rw "Interrupt Mask bit 63"; 91 mirq62 1 rw "Interrupt Mask bit 62"; 92 mirq61 1 rw "Interrupt Mask bit 61"; 93 mirq60 1 rw "Interrupt Mask bit 60"; 94 mirq59 1 rw "Interrupt Mask bit 59"; 95 mirq58 1 rw "Interrupt Mask bit 58"; 96 mirq57 1 rw "Interrupt Mask bit 57"; 97 mirq56 1 rw "Interrupt Mask bit 56"; 98 _ 1 mbz; 99 mirq54 1 rw "Interrupt Mask bit 54"; 100 mirq53 1 rw "Interrupt Mask bit 53"; 101 mirq52 1 rw "Interrupt Mask bit 52"; 102 mirq51 1 rw "Interrupt Mask bit 51"; 103 mirq50 1 rw "Interrupt Mask bit 50"; 104 _ 1 mbz; 105 mirq48 1 rw "Interrupt Mask bit 48"; 106 mirq47 1 rw "Interrupt Mask bit 47"; 107 mirq46 1 rw "Interrupt Mask bit 46"; 108 _ 3 mbz; 109 mirq42 1 rw "Interrupt Mask bit 42"; 110 mirq41 1 rw "Interrupt Mask bit 41"; 111 mirq40 1 rw "Interrupt Mask bit 40"; 112 mirq39 1 rw "Interrupt Mask bit 39"; 113 mirq38 1 rw "Interrupt Mask bit 38"; 114 mirq37 1 rw "Interrupt Mask bit 37"; 115 mirq36 1 rw "Interrupt Mask bit 36"; 116 mirq35 1 rw "Interrupt Mask bit 35"; 117 mirq34 1 rw "Interrupt Mask bit 34"; 118 mirq33 1 rw "Interrupt Mask bit 33"; 119 _ 1 mbz; 120 }; 121};