1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_c2c_slave_niu_firewall.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_c2c_slave_niu_firewall msbfirst ( addr base ) "" {
29    
30    
31    register error_log_k addr(base, 0x0) "Error log register for port k" {
32        _ 8 mbz;
33        blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
34        _ 1 mbz;
35        region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
36        region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
37        reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers";
38    };
39    
40    register logical_addr_errlog_k ro addr(base, 0x20004) "Logical Physical Address Error log register for port k" type(uint32);
41    
42    register regupdate_control addr(base, 0x20040) "Register update control register" {
43        _ 30 mbz;
44        fw_load_req 1 ro "Hadrdware set/Software clear";
45        busy_req 1 rw "Busy request";
46    };
47    
48    register mrm_permission_region_low_j_0 addr(base, 0x20088) "Region j Permission Low" {
49        _ 1 rsvd;
50        _ 1 rsvd;
51        _ 1 rsvd;
52        _ 1 rsvd;
53        _ 1 rsvd;
54        _ 1 rsvd;
55        _ 1 rsvd;
56        _ 1 rsvd;
57        _ 1 rsvd;
58        _ 1 rsvd;
59        _ 1 rsvd;
60        _ 1 rsvd;
61        _ 1 rsvd;
62        _ 1 rsvd;
63        _ 1 rsvd;
64        _ 1 rsvd;
65        pub_prv_debug 1 rw "Public Privilege Debug Allowed";
66        pub_usr_debug 1 rw "Public User Debug Allowed";
67        _ 1 rsvd;
68        _ 1 rsvd;
69        pub_prv_write 1 rw "Public Privilege Write Allowed";
70        pub_prv_read 1 rw "Public Privilege Read Allowed";
71        pub_prv_exe 1 rw "Public Privilege Exe Allowed";
72        pub_usr_write 1 rw "Public User Write Access Allowed";
73        pub_usr_read 1 rw "Public User Read Access Allowed";
74        pub_usr_exe 1 rw "Public User Exe Access Allowed";
75        _ 1 rsvd;
76        _ 1 rsvd;
77        _ 1 rsvd;
78        _ 1 rsvd;
79        _ 1 rsvd;
80        _ 1 rsvd;
81    };
82    
83    register mrm_permission_region_low_j_1 addr(base, 0x20098) "Region j Permission Low" {
84        _ 1 rsvd;
85        _ 1 rsvd;
86        _ 1 rsvd;
87        _ 1 rsvd;
88        _ 1 rsvd;
89        _ 1 rsvd;
90        _ 1 rsvd;
91        _ 1 rsvd;
92        _ 1 rsvd;
93        _ 1 rsvd;
94        _ 1 rsvd;
95        _ 1 rsvd;
96        _ 1 rsvd;
97        _ 1 rsvd;
98        _ 1 rsvd;
99        _ 1 rsvd;
100        pub_prv_debug 1 rw "Public Privilege Debug Allowed";
101        pub_usr_debug 1 rw "Public User Debug Allowed";
102        _ 1 rsvd;
103        _ 1 rsvd;
104        pub_prv_write 1 rw "Public Privilege Write Allowed";
105        pub_prv_read 1 rw "Public Privilege Read Allowed";
106        pub_prv_exe 1 rw "Public Privilege Exe Allowed";
107        pub_usr_write 1 rw "Public User Write Access Allowed";
108        pub_usr_read 1 rw "Public User Read Access Allowed";
109        pub_usr_exe 1 rw "Public User Exe Access Allowed";
110        _ 1 rsvd;
111        _ 1 rsvd;
112        _ 1 rsvd;
113        _ 1 rsvd;
114        _ 1 rsvd;
115        _ 1 rsvd;
116    };
117    
118    register mrm_permission_region_low_j_2 addr(base, 0x200A8) "Region j Permission Low" {
119        _ 1 rsvd;
120        _ 1 rsvd;
121        _ 1 rsvd;
122        _ 1 rsvd;
123        _ 1 rsvd;
124        _ 1 rsvd;
125        _ 1 rsvd;
126        _ 1 rsvd;
127        _ 1 rsvd;
128        _ 1 rsvd;
129        _ 1 rsvd;
130        _ 1 rsvd;
131        _ 1 rsvd;
132        _ 1 rsvd;
133        _ 1 rsvd;
134        _ 1 rsvd;
135        pub_prv_debug 1 rw "Public Privilege Debug Allowed";
136        pub_usr_debug 1 rw "Public User Debug Allowed";
137        _ 1 rsvd;
138        _ 1 rsvd;
139        pub_prv_write 1 rw "Public Privilege Write Allowed";
140        pub_prv_read 1 rw "Public Privilege Read Allowed";
141        pub_prv_exe 1 rw "Public Privilege Exe Allowed";
142        pub_usr_write 1 rw "Public User Write Access Allowed";
143        pub_usr_read 1 rw "Public User Read Access Allowed";
144        pub_usr_exe 1 rw "Public User Exe Access Allowed";
145        _ 1 rsvd;
146        _ 1 rsvd;
147        _ 1 rsvd;
148        _ 1 rsvd;
149        _ 1 rsvd;
150        _ 1 rsvd;
151    };
152    
153    register mrm_permission_region_low_j_3 addr(base, 0x200B8) "Region j Permission Low" {
154        _ 1 rsvd;
155        _ 1 rsvd;
156        _ 1 rsvd;
157        _ 1 rsvd;
158        _ 1 rsvd;
159        _ 1 rsvd;
160        _ 1 rsvd;
161        _ 1 rsvd;
162        _ 1 rsvd;
163        _ 1 rsvd;
164        _ 1 rsvd;
165        _ 1 rsvd;
166        _ 1 rsvd;
167        _ 1 rsvd;
168        _ 1 rsvd;
169        _ 1 rsvd;
170        pub_prv_debug 1 rw "Public Privilege Debug Allowed";
171        pub_usr_debug 1 rw "Public User Debug Allowed";
172        _ 1 rsvd;
173        _ 1 rsvd;
174        pub_prv_write 1 rw "Public Privilege Write Allowed";
175        pub_prv_read 1 rw "Public Privilege Read Allowed";
176        pub_prv_exe 1 rw "Public Privilege Exe Allowed";
177        pub_usr_write 1 rw "Public User Write Access Allowed";
178        pub_usr_read 1 rw "Public User Read Access Allowed";
179        pub_usr_exe 1 rw "Public User Exe Access Allowed";
180        _ 1 rsvd;
181        _ 1 rsvd;
182        _ 1 rsvd;
183        _ 1 rsvd;
184        _ 1 rsvd;
185        _ 1 rsvd;
186    };
187    
188    register mrm_permission_region_high_j_0 addr(base, 0x2008C) "Region j Permission High" {
189        _ 6 rsvd;
190        w12 1 rw "Master NIU ConnID = 12 write permission";
191        r12 1 rw "Master NIU ConnID = 12 read permission";
192        _ 1 rsvd;
193        _ 1 rsvd;
194        w10 1 rw "Master NIU ConnID = 10 write permission";
195        r10 1 rw "Master NIU ConnID = 10 read permission";
196        w9 1 rw "Master NIU ConnID = 9 write permission";
197        r9 1 rw "Master NIU ConnID = 9 read permission";
198        w8 1 rw "Master NIU ConnID = 8 write permission";
199        r8 1 rw "Master NIU ConnID = 8 read permission";
200        w7 1 rw "Master NIU ConnID = 7 write permission";
201        r7 1 rw "Master NIU ConnID = 7 read permission";
202        w6 1 rw "Master NIU ConnID = 6 write permission";
203        r6 1 rw "Master NIU ConnID = 6 read permission";
204        w5 1 rw "Master NIU ConnID = 5 write permission";
205        r5 1 rw "Master NIU ConnID = 5 read permission";
206        w4 1 rw "Master NIU ConnID = 4 write permission";
207        r4 1 rw "Master NIU ConnID = 4 read permission";
208        w3 1 rw "Master NIU ConnID = 3 write permission";
209        r3 1 rw "Master NIU ConnID = 3 read permission";
210        w2 1 rw "Master NIU ConnID = 2 write permission";
211        r2 1 rw "Master NIU ConnID = 2 read permission";
212        w1 1 rw "Master NIU ConnID = 1 write permission";
213        r1 1 rw "Master NIU ConnID = 1 read permission";
214        w0 1 rw "Master NIU ConnID = 0 write permission";
215        r0 1 rw "Master NIU ConnID = 0 read permission";
216    };
217    
218    register mrm_permission_region_high_j_1 addr(base, 0x2009C) "Region j Permission High" {
219        _ 6 rsvd;
220        w12 1 rw "Master NIU ConnID = 12 write permission";
221        r12 1 rw "Master NIU ConnID = 12 read permission";
222        _ 1 rsvd;
223        _ 1 rsvd;
224        w10 1 rw "Master NIU ConnID = 10 write permission";
225        r10 1 rw "Master NIU ConnID = 10 read permission";
226        w9 1 rw "Master NIU ConnID = 9 write permission";
227        r9 1 rw "Master NIU ConnID = 9 read permission";
228        w8 1 rw "Master NIU ConnID = 8 write permission";
229        r8 1 rw "Master NIU ConnID = 8 read permission";
230        w7 1 rw "Master NIU ConnID = 7 write permission";
231        r7 1 rw "Master NIU ConnID = 7 read permission";
232        w6 1 rw "Master NIU ConnID = 6 write permission";
233        r6 1 rw "Master NIU ConnID = 6 read permission";
234        w5 1 rw "Master NIU ConnID = 5 write permission";
235        r5 1 rw "Master NIU ConnID = 5 read permission";
236        w4 1 rw "Master NIU ConnID = 4 write permission";
237        r4 1 rw "Master NIU ConnID = 4 read permission";
238        w3 1 rw "Master NIU ConnID = 3 write permission";
239        r3 1 rw "Master NIU ConnID = 3 read permission";
240        w2 1 rw "Master NIU ConnID = 2 write permission";
241        r2 1 rw "Master NIU ConnID = 2 read permission";
242        w1 1 rw "Master NIU ConnID = 1 write permission";
243        r1 1 rw "Master NIU ConnID = 1 read permission";
244        w0 1 rw "Master NIU ConnID = 0 write permission";
245        r0 1 rw "Master NIU ConnID = 0 read permission";
246    };
247    
248    register mrm_permission_region_high_j_2 addr(base, 0x200AC) "Region j Permission High" {
249        _ 6 rsvd;
250        w12 1 rw "Master NIU ConnID = 12 write permission";
251        r12 1 rw "Master NIU ConnID = 12 read permission";
252        _ 1 rsvd;
253        _ 1 rsvd;
254        w10 1 rw "Master NIU ConnID = 10 write permission";
255        r10 1 rw "Master NIU ConnID = 10 read permission";
256        w9 1 rw "Master NIU ConnID = 9 write permission";
257        r9 1 rw "Master NIU ConnID = 9 read permission";
258        w8 1 rw "Master NIU ConnID = 8 write permission";
259        r8 1 rw "Master NIU ConnID = 8 read permission";
260        w7 1 rw "Master NIU ConnID = 7 write permission";
261        r7 1 rw "Master NIU ConnID = 7 read permission";
262        w6 1 rw "Master NIU ConnID = 6 write permission";
263        r6 1 rw "Master NIU ConnID = 6 read permission";
264        w5 1 rw "Master NIU ConnID = 5 write permission";
265        r5 1 rw "Master NIU ConnID = 5 read permission";
266        w4 1 rw "Master NIU ConnID = 4 write permission";
267        r4 1 rw "Master NIU ConnID = 4 read permission";
268        w3 1 rw "Master NIU ConnID = 3 write permission";
269        r3 1 rw "Master NIU ConnID = 3 read permission";
270        w2 1 rw "Master NIU ConnID = 2 write permission";
271        r2 1 rw "Master NIU ConnID = 2 read permission";
272        w1 1 rw "Master NIU ConnID = 1 write permission";
273        r1 1 rw "Master NIU ConnID = 1 read permission";
274        w0 1 rw "Master NIU ConnID = 0 write permission";
275        r0 1 rw "Master NIU ConnID = 0 read permission";
276    };
277    
278    register mrm_permission_region_high_j_3 addr(base, 0x200BC) "Region j Permission High" {
279        _ 6 rsvd;
280        w12 1 rw "Master NIU ConnID = 12 write permission";
281        r12 1 rw "Master NIU ConnID = 12 read permission";
282        _ 1 rsvd;
283        _ 1 rsvd;
284        w10 1 rw "Master NIU ConnID = 10 write permission";
285        r10 1 rw "Master NIU ConnID = 10 read permission";
286        w9 1 rw "Master NIU ConnID = 9 write permission";
287        r9 1 rw "Master NIU ConnID = 9 read permission";
288        w8 1 rw "Master NIU ConnID = 8 write permission";
289        r8 1 rw "Master NIU ConnID = 8 read permission";
290        w7 1 rw "Master NIU ConnID = 7 write permission";
291        r7 1 rw "Master NIU ConnID = 7 read permission";
292        w6 1 rw "Master NIU ConnID = 6 write permission";
293        r6 1 rw "Master NIU ConnID = 6 read permission";
294        w5 1 rw "Master NIU ConnID = 5 write permission";
295        r5 1 rw "Master NIU ConnID = 5 read permission";
296        w4 1 rw "Master NIU ConnID = 4 write permission";
297        r4 1 rw "Master NIU ConnID = 4 read permission";
298        w3 1 rw "Master NIU ConnID = 3 write permission";
299        r3 1 rw "Master NIU ConnID = 3 read permission";
300        w2 1 rw "Master NIU ConnID = 2 write permission";
301        r2 1 rw "Master NIU ConnID = 2 read permission";
302        w1 1 rw "Master NIU ConnID = 1 write permission";
303        r1 1 rw "Master NIU ConnID = 1 read permission";
304        w0 1 rw "Master NIU ConnID = 0 write permission";
305        r0 1 rw "Master NIU ConnID = 0 read permission";
306    };
307};