1/* 2 * Copyright (c) 2009, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * lpuart.dev 11 * 12 * DESCRIPTION: Low Power UART 13 * 14 * This is derived from: 15 * 16 * i.MX 8DualXPlus Appliacations Processor Reference Manual, revision D, NXP 17 * Pages 2255 - 2298 18 * (IMX8DQXPRM.pdf) 19 * 20 */ 21 22device lpuart msbfirst (addr base) "LPUART" { 23 24 constants feature "feature set number" { 25 standard = 0b01 "Standard feature set"; 26 irda = 0b11 "Standard feature set with MODEM/IrDA support"; 27 }; 28 29 constants trgsel "trigger select" { 30 disabled = 0b00 "Input trigger is disabled."; 31 rx = 0b01 "Input trigger is used instead of RX pin input."; 32 ctsb = 0b10 "Input trigger is used instead of CTS_B pin input.`"; 33 modrx = 0b11 "Input trigger is used to modulate TX pin output."; 34 }; 35 36 constants osr "oversampling ratio" { 37 default = 0b00000 "Writing 0 to this field will result in an oversampling ratio of 16."; 38 ratio4 = 0b00011 "Oversampling ratio of 4, requires BOTHEDGE to be set."; 39 ratio5 = 0b00100 "Oversampling ratio of 5, requires BOTHEDGE to be set."; 40 ratio6 = 0b00101 "Oversampling ratio of 6, requires BOTHEDGE to be set."; 41 ratio7 = 0b00110 "Oversampling ratio of 7, requires BOTHEDGE to be set."; 42 ratio8 = 0b00111 "Oversampling ratio of 8."; 43 ratio9 = 0b01000 "Oversampling ratio of 9."; 44 ratio10 = 0b01001 "Oversampling ratio of 10."; 45 ratio11 = 0b01010 "Oversampling ratio of 11."; 46 ratio12 = 0b01011 "Oversampling ratio of 12."; 47 ratio13 = 0b01100 "Oversampling ratio of 13."; 48 ratio14 = 0b01101 "Oversampling ratio of 14."; 49 ratio15 = 0b01110 "Oversampling ratio of 15."; 50 ratio16 = 0b01111 "Oversampling ratio of 16."; 51 ratio17 = 0b10000 "Oversampling ratio of 17."; 52 ratio18 = 0b10001 "Oversampling ratio of 18."; 53 ratio19 = 0b10010 "Oversampling ratio of 19."; 54 ratio20 = 0b10011 "Oversampling ratio of 20."; 55 ratio21 = 0b10100 "Oversampling ratio of 21."; 56 ratio22 = 0b10101 "Oversampling ratio of 22."; 57 ratio23 = 0b10110 "Oversampling ratio of 23."; 58 ratio24 = 0b10111 "Oversampling ratio of 24."; 59 ratio25 = 0b11000 "Oversampling ratio of 25."; 60 ratio26 = 0b11001 "Oversampling ratio of 26."; 61 ratio27 = 0b11010 "Oversampling ratio of 27."; 62 ratio28 = 0b11011 "Oversampling ratio of 28."; 63 ratio29 = 0b11100 "Oversampling ratio of 29."; 64 ratio30 = 0b11101 "Oversampling ratio of 30."; 65 ratio31 = 0b11110 "Oversampling ratio of 31."; 66 ratio32 = 0b11111 "Oversampling ratio of 32."; 67 }; 68 69 register verid ro addr(base, 0x0) "Version ID Register" { 70 major 8 "Major Version Number"; 71 minor 8 "Minor Version Number"; 72 feature 16 type(feature) "Feature Identification Number"; 73 }; 74 75 register param ro addr(base, 0x4) "Parameter Register" { 76 _ 16; 77 rxfifo 8 "Receive FIFO size (2^RXFIFO)"; 78 txfifo 8 "Transmit FIFO size (2^FIFO)"; 79 }; 80 81 register global ro addr(base, 0x8) "LPUART Global Register" { 82 _ 30; 83 rst 1 rw "Software Reset"; 84 _ 1; 85 }; 86 87 register pincfg addr(base, 0xc) "LPUART Pin Configuration Register" { 88 _ 30; 89 trgsel 2 rw type(trgsel) "Trigger select"; 90 }; 91 92 register baud addr(base, 0x10) "LPUART Baud Rate Register" { 93 maen1 1 "Match address mode enable 1"; 94 maen2 1 "Match address mode enable 2"; 95 m10 1 "10-bit mode select"; 96 osr 5 type(osr) "Oversampling ratio"; 97 tdmae 1 "Transmitter DMA Enable"; 98 _ 1; 99 rdmae 1 "Receiver Full DMA Enable"; 100 ridmae 1 "Receiver idle DMA Enable"; 101 matcfg 2 "Match Configuration"; 102 bothedge 1 "Both Edge Sampling"; 103 resynccdis 1 "Resynchronization Disable"; 104 lbkdie 1 "LIN Break Detect Interrupt Enable"; 105 rxedgie 1 "RX Input Active Edge Interrupt Enable"; 106 sbns 1 "Stop Bit Number Select"; 107 sbr 13 "Baud Rate Modulo Divisor"; 108 }; 109 110 register stat addr(base, 0x14) "LPUART Status Register" { 111 lbkdif 1 rw1c "LIN Break Detect Interrupt flag"; 112 rxedgif 1 rw1c "RX Pin Active Edge Interrupt Flag"; 113 msbf 1 "MSB first"; 114 rxinv 1 "Receive Data Inversion"; 115 rwuid 1 "Whether idle char sets IDLE bit."; 116 brk13 1 "Break Character Generation Length"; 117 lbkde 1 "LIN Break Detection Enable"; 118 raf 1 ro "Receiver Active Flag"; 119 tdre 1 ro "Transmit Data Register Empty Flag"; 120 tc 1 ro "Transmit Complete Flag"; 121 rdrf 1 ro "Receive Data Register Full Flag"; 122 idle 1 rw1c "Idle Line Flag"; 123 or 1 rw1c "Receiver Overrun Flag"; 124 nf 1 rw1c "Noise Flag"; 125 fe 1 rw1c "Framing Error Flag"; 126 pf 1 rw1c "Parity Error Flag"; 127 ma1f 1 rw1c "Match 1 Flag"; 128 ma2f 1 rw1c "Match 2 Flag"; 129 _ 14; 130 }; 131 132 register ctrl addr(base, 0x18) "LPUART Control Register" { 133 r8t9 1 "Receive Bit 8 / Transmit Bit 9"; 134 r9t8 1 "Receive Bit 9 / Transmit Bit 8"; 135 txdir 1 "TX Pin Direction Single-Wire Mode"; 136 txinv 1 "Transmit Data Inversion"; 137 orie 1 "Overrrun Interrupt Enable"; 138 neie 1 "Noise Error Interrupt Enable"; 139 feie 1 "Framing Error Interrupt Enable"; 140 peie 1 "Parity Error Interrupt Enable"; 141 tie 1 "Transmit Interrupt Enable"; 142 tcie 1 "Transmission Complete Interrupt Enable"; 143 rie 1 "Receiver Interrupt Enable"; 144 iue 1 "Idle Line Interrupt Enable"; 145 te 1 "Transmitter Enable"; 146 re 1 "Receiver Enable"; 147 rwu 1 "Receiver Wakeup Control"; 148 sbk 1 "Send Break"; 149 ma1ie 1 "Match 1 Interrupt Enable"; 150 ma2ie 1 "Match 2 Interrupt Enable"; 151 _ 2; 152 m7 1 "7-Bit Mode Select"; 153 idlecfg 3 "Idle Configuration (2^IDLECFG idle characters before IDLE flag set)"; 154 loops 1 "Loop Mode Select"; 155 dozeen 1 "Doze Enable"; 156 rsrc 1 "Receiver Source Select"; 157 m 1 "9-Bit or 8-Bit Mode Select"; 158 wake 1 "Receiver Wakeup Method Select"; 159 ilt 1 "Idle Line Type Select"; 160 pe 1 "Parity Enable"; 161 pt 1 "Parity Type"; 162 }; 163 164 /* 165 * Data register is actually two registers for RX/TX 166 * To prevent Mackerel from generating code for reading 167 * things via the TX register and therefore clearing the RX 168 * register we declare the readonly fields as mbz in the TX 169 * register. 170 */ 171 register rxdata ro addr(base, 0x1c) "LPUART Receive Data Register" { 172 _ 16; 173 noisy 1 "Whether received with noise."; 174 paritye 1 "Whether received with parity error."; 175 fre 1 "Whether received with frame error"; 176 rxempt 1 "Receive Buffer Empty"; 177 idline 1 "Idle Line"; 178 _ 1; 179 buf 10 "Data buffer"; 180 }; 181 182 register txdata wo also addr(base, 0x1c) "LPUART Transmit Data Register" { 183 _ 16 mbz; 184 _ 1 mbz; 185 _ 1 mbz; 186 tsc 1 "Transmit Special Character"; 187 _ 1 mbz; 188 _ 1 mbz; 189 _ 1 mbz; 190 buf 10 "Data buffer"; 191 }; 192 193 register match addr(base, 0x20) "LPUART Match Address Register" { 194 _ 6; 195 ma2 10 "Match Address 2"; 196 _ 6; 197 ma1 10 "Match Address 1"; 198 }; 199 200 register modir addr(base, 0x24) "LPUART Modem IrDA Register" { 201 _ 13; 202 iren 1 "Infrared enable"; 203 tnp 2 "Transmitter narrow pulse"; 204 _ 2; 205 rtswater 6 "Receive RTS Configuration"; 206 _ 2; 207 txctssrc 1 "Transmit CTS Source"; 208 txctsc 1 "Transmit CTS Configuration"; 209 rxrtse 1 "Receiver request-to-send enable"; 210 txrtspol 1 "Transmitter request-to-send polarity"; 211 txrtse 1 "Transmitter request-to-send enable"; 212 txctse 1 "Transmitter clear-to-send enable"; 213 }; 214 215 register fifo addr(base, 0x28) "LPUART FIFO Register" { 216 _ 8; 217 txempt 1 ro "Transmit Buffer/FIFO Empty"; 218 rxempt 1 ro "Receive Buffer/FIFO Empty"; 219 _ 4; 220 txof 1 rw1c "Trasnmitter Buffer Overflow Flag"; 221 rxuf 1 rw1c "Receiver Buffer Underflow Flag"; 222 txflush 1 wo "Transmit FIFO/Buffer Flush"; 223 rxflush 1 wo "Receive FIFO/Buffer Flush"; 224 _ 1; 225 rxiden 3 "Receiver Idle Empty Enable"; 226 txofe 1 "Transmit FIFO Overflow Interrupt Enable"; 227 rxufe 1 "Receive FIFO Underflow Interrupt Enable"; 228 txfe 1 "Transmit FIFO Enable"; 229 txfifosize 3 ro "Transmit FIFO Buffer Depth"; 230 rxfe 1 "Receive FIFO Enable"; 231 rxfifosize 3 ro "Receive FIFO Buffer Depth"; 232 }; 233 234 register water addr(base, 0x2c) "LPUART Watemark Register" { 235 _ 1; 236 rxcount 7 ro "Receive Counter"; 237 _ 2; 238 rxwater 6 "Receiver Watermark"; 239 _ 1; 240 txcount 7 ro "Transmit Counter"; 241 _ 2; 242 txwater 6 "Transmit Watermark"; 243 }; 244}; 245