1/* 2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * lpc_timer.dev 11 * 12 * DESCRIPTION: Legacy timer registers on the LPC (low pin count, or 13 * legacy PC) bridge function of a typical Intel IHC 14 * (Southbridge). 15 * 16 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub 17 * Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)". 18 */ 19 20device lpc_timer (io base) "LPC Timer" { 21 // 22 // Section 21.3: Timer I/O registers 23 // 24 25 constants cnt_mode "Counter mode" { 26 oseoc = 0b000 "Out signal on end of count (mode 0)"; 27 hr1s = 0b001 "Hardware retriggerable one-shot (mode 1)"; 28 rtgen = 0b010 "Rate generator (mode 2)"; 29 rtgen_ = 0b110 "Rate generator (mode 2)"; 30 sqwav = 0b011 "Square wave output (mode 3)"; 31 sqwav_ = 0b111 "Square wave output (mode 3)"; 32 swstr = 0b100 "Software triggered strobe (mode 4)"; 33 hwstr = 0b101 "Hardware triggered strobe (mode 5)"; 34 }; 35 36 constants timer_rwsel "Read/write select" { 37 clc = 0b00 "Counter latch cmd"; 38 lsb = 0b01 "R/w least sig. byte"; 39 msb = 0b10 "R/w most sig. byte"; 40 lmsb = 0b11 "R/w lsb then msb"; 41 }; 42 43 constants timer_cntsel "Counter select" { 44 c0 = 0b00 "Counter 0"; 45 c1 = 0b01 "Counter 1"; 46 c2 = 0b10 "Counter 2"; 47 rb = 0b11 "Read back cmd"; 48 }; 49 50 register tcw wo io( base, 0x3 ) "Timer Control Word" { 51 bcd 1 "Binary coded decimal select"; 52 mode 3 type(cnt_mode) "Counter mode"; 53 rwsel 2 type(timer_rwsel) "Read/write select"; 54 select 2 type(timer_cntsel) "Counter select"; 55 }; 56 57 register rdbk_cmd wo also io( base, 0x3 ) "Read back command" { 58 _ 1 mbz; 59 c0 1 "Counter 0 select"; 60 c1 1 "Counter 1 select"; 61 c2 1 "Counter 2 select"; 62 stat 1 "Latch status of selected counters"; 63 count 1 "Latch count of selected counters"; 64 _ 2 mb1; 65 }; 66 67 register ltch_cmd wo also io( base, 0x3 ) "Counter latch command" { 68 _ 6 mbz; 69 select 2 type(timer_cntsel) "Counter select"; 70 }; 71 72 regtype sbyte_fmt "Interval timer status byte format" { 73 bcd 1 "Binary coded decimal select"; 74 mode 3 type(cnt_mode) "Counter mode"; 75 rwsel 2 type(timer_rwsel) "Read/write select"; 76 cnt_stat 1 "Count register status"; 77 cnt_out 1 "Counter OUT pin status"; 78 }; 79 register sbyte_fmt0 ro io( base, 0x0 ) "Int. timer 0 status format" type(sbyte_fmt); 80 81 register sbyte_fmt1 ro io( base, 0x1 ) "Int. timer 1 status format" type(sbyte_fmt); 82 register sbyte_fmt2 ro io( base, 0x2 ) "Int. timer 2 status format" type(sbyte_fmt); 83 84 register cntacc0 rw also io( base, 0x0 ) "Counter 0 access" type(uint8); 85 register cntacc1 rw also io( base, 0x1 ) "Counter 1 access" type(uint8); 86 register cntacc2 rw also io( base, 0x2 ) "Counter 2 access" type(uint8); 87 88}; 89