1/*
2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * lpc_rtc.dev
11 *
12 * DESCRIPTION: Legacy real-time clock registers on the LPC (low pin count, or
13 *              legacy PC) bridge function of a typical Intel IHC
14 *              (Southbridge).    
15 * 
16 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
17 * Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)". 
18 * 
19 */
20
21device LPC_rtc (io base) "LPC Real-Time Clock" {
22  
23  // 21.6
24  // 
25  // We have two register spaces: standard, and extended.  They use
26  // different index and target registers. 
27  // 
28  space std(addr) valuewise "Standard register space";
29  register ndx rw io(base, 0x70) "Standard index" type(uint8);
30  register target rw io(base, 0x71) "Standard target" type(uint8);
31  regarray standard rw std(0x00)[256] type(uint8);
32
33  space ext(addr) valuewise "Extended register space"; 
34  register endx rw io(base, 0x72) "Extended index" type(uint8);
35  register etarget rw io(base, 0x73) "Extended target" type(uint8);
36  regarray extended rw ext(0x00)[256] type(uint8);
37
38  // 21.6.2
39  register seconds    rw also std(0x0) "Seconds" type(uint8);
40  register al_seconds rw also std(0x1) "Seconds alarm" type(uint8);
41  register minutes    rw also std(0x2) "Minutes" type(uint8);
42  register al_minutes rw also std(0x3) "Minutes Alarm" type(uint8);
43  register hours      rw also std(0x4) "Hours" type(uint8);
44  register al_hours   rw also std(0x5) "Hours Alarm" type(uint8);
45  register weekday    rw also std(0x6) "Day of Week" type(uint8);
46  register date       rw also std(0x7) "Day of Month" type(uint8);
47  register month      rw also std(0x8) "Month" type(uint8);
48  register year       rw also std(0x9) "Year" type(uint8);
49
50  // 21.6.2.1
51  constants dcs "Division chain select" {
52    normal	= 0b010 "Normal operation";
53    divreset	= 0b110 "Divider reset";
54    divreset2	= 0b111 "Divider reset";
55    bypass15	= 0b101 "Bypass 15 stages";
56    bypass10	= 0b100 "Bypass 10 stages";
57    bypass5	= 0b011 "Bypass 5 stages";
58  };
59  
60  constants rate "Rate select" {
61    never	= 0b0000 "Interrupt never toggles";
62    ms3_90625_	= 0b0001 "3.90625 ms (duplicate)";
63    ms7_8125_	= 0b0010 "7.8125 ms (duplicate)";
64    us122_070	= 0b0011 "122.070 us";
65    us244_141	= 0b0100 "244.141 us";
66    us488_281	= 0b0101 "488.281 us";
67    us976_5625	= 0b0110 "976.5625 us";
68    ms1_953125	= 0b0111 "1.953125 ms";
69    ms3_906251	= 0b1000 "3.906251 ms";
70    ms7_8125	= 0b1001 "7.8125 ms";
71    ms15_625	= 0b1010 "15.625 ms";
72    ms31_25	= 0b1011 "31.25 ms";
73    ms62_5	= 0b1100 "62.5 ms";
74    ms125	= 0b1101 "125 ms";
75    ms250	= 0b1110 "250 ms";
76    ms500	= 0b1111 "500 ms";
77  };
78
79  register rega rw also std(0xa) "Register A" {
80    rs		4 type(rate) "Rate select";
81    dv		3 type(dcs) "Divisioin chain select";
82    uip		1 "Update in progress";
83  };
84
85  // 26.6.2.2
86  register regb rw also std(0xb) "General configuration" {
87    dse		1 "Daylight savings enable";
88    hourform	1 "Hour format";
89    dm		1 "Data mode (BCD/binary)";
90    sqwe	1 "Square wave enable";
91    uie		1 "Update-ended interrupt enable";
92    aie		1 "Alarm interrupt enable";
93    pie		1 "Periodic interrupt enable";
94    set		1 "Update cycle inhibit";
95  };
96
97  // 26.6.2.3
98  register regc ro also std(0xc) "Flag register C" {
99    _		4;
100    uf		1 "Update-ended";
101    af		1 "Alarm";
102    pf		1 "Periodic interrupt";
103    irqf	1 "Interrupt request flag";
104  };
105
106  // 26.6.2.4
107  register regd rw also std(0xd) "Flag register D" {
108    al_date	6 "Date alarm";
109    _		1;
110    vrt		1 mbz "Valid RAM and time";
111  };
112
113};
114
115
116  
117