1/* 2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * lpc_pic.dev 11 * 12 * DESCRIPTION: Definition of the LPC (low pin count, or legacy PC) 13 * bridge function of a typical Intel IHC (Southbridge). 14 * 15 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub 16 * Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)". 17 * 18 */ 19 20device lpc_pic lsbfirst (io base) "LPC IHC PIC function" { 21 // 22 // 8259 PIC registers: section 21.4 23 // 24 25 constants rrc "Register read command" { 26 read_irq = 0b10 "Read IRQ register"; 27 read_is = 0b11 "Read IS register"; 28 }; 29 30 constants rsleoi "Rotate and EOI codes" { 31 raeoic = 0b000 "Rotate in auto EOI mode (clear)"; 32 eoi = 0b001 "Non-specific EOI command"; 33 seoi = 0b011 "Specific EOI command"; 34 raeois = 0b100 "Rotate in auto EOI mode (set)"; 35 reoi = 0b101 "Rotate on non-specific EOI command"; 36 sp = 0b110 "Set priority command"; 37 rseoi = 0b111 "Rotate on specific EOI command"; 38 }; 39 40 regtype icw1 "Initialization Command Word 1" { 41 _ 1 mb1; 42 _ 1 mbz; // Specify cascade mode 43 _ 1 mbz; 44 ltim 1 "Edge / Level bank select (ignored)"; 45 _ 1 mb1; 46 _ 3 mbz; 47 }; 48 49 regtype icw2 "Initialization Command Word 2" { 50 req_level 3 "Interrupt request level"; 51 base 5 "Interrupt vector base address"; 52 }; 53 54 regtype pic_master_icw3 "Master Controller Initialization Command Word 3" { 55 _ 2 mbz; 56 cascade 1 "Cascaded PIC IRQ connection"; 57 _ 5 mbz; 58 }; 59 60 regtype pic_slave_icw3 "Slave Controller Initialization Command Word 3" { 61 slave_id 3 "Slave Identification Code"; 62 _ 5 mbz; 63 }; 64 65 regtype icw4 "Initialization Command Word 4" { 66 _ 1 mb1; 67 aeoi 1 "Automatic End of Interrupt"; 68 _ 1 mbz; 69 _ 1 mbz; 70 sfnm 1 "Special fully nested mode"; 71 _ 3 mbz; 72 }; 73 74/* 75 regtype ocw1 "Operational Control Word 1 (Interrupt Mask)" { 76 irq_mask 8 type(uint8) "Interrupt request mask"; 77 }; 78*/ 79 80 regtype ocw2 "Operational Control Word 2" { 81 level 3 "Interrupt level select"; 82 _ 2 mbz; 83 rsleoi 3 type(rsleoi) "Rotate and EOI Codes"; 84 }; 85 86 regtype ocw3 "Operational Control Word 3" { 87 rrc 2 type(rrc) "Register read command"; 88 pmc 1 "Poll mode command"; 89 _ 1 mb1; 90 _ 1 mbz; 91 esmm 1 "Enable special mask mode"; 92 smm 1 "Special mask mode"; 93 _ 1 mbz; 94 }; 95 96 regtype pic_master_trigger "Master Controller Edge/Level Triggered" { 97 _ 3 mbz; 98 irq3_ecl 1 "IRQ3 ECL"; 99 irq4_ecl 1 "IRQ4 ECL"; 100 irq5_ecl 1 "IRQ5 ECL"; 101 irq6_ecl 1 "IRQ6 ECL"; 102 irq7_ecl 1 "IRQ7 ECL"; 103 }; 104 105 regtype pic_slave_trigger "Slave Controller Edge/Level Triggered" { 106 _ 1 mbz; 107 irq9_ecl 1 "IRQ9 ECL"; 108 irq10_ecl 1 "IRQ10 ECL"; 109 irq11_ecl 1 "IRQ11 ECL"; 110 irq12_ecl 1 "IRQ12 ECL"; 111 _ 1 mbz; 112 irq14_ecl 1 "IRQ14 ECL"; 113 irq15_ecl 1 "IRQ15 ECL"; 114 }; 115 116 register master_icw1 wo io( base, 0x20 ) "Master PIC Initialization Command Word 1" type(icw1); 117 register master_ocw2 wo also io( base, 0x20 ) "Master PIC Op Ctrl Word 2" type(ocw2); 118 register master_ocw3 wo also io( base, 0x20 ) "Master PIC Op Ctrl Word 3" type(ocw3); 119 register master_ocw3rd ro also io( base, 0x20 ) "Master PIC Op Ctrl Word 3" type(uint8); 120 121 register master_icw2 wo io( base, 0x21 ) "Master PIC Initialization Command Word 2" type(icw2); 122 register master_icw3 wo also io( base, 0x21 ) "Master PIC Initialization Command Word 3" type(pic_master_icw3); 123 register master_icw4 wo also io( base, 0x21 ) "Master PIC Initialization Command Word 4" type(icw4); 124 register master_ocw1 rw also io( base, 0x21 ) "Master PIC Operation Control Word 1" type(uint8); 125 126 register slave_icw1 wo io( base, 0xa0 ) "Slave PIC Initialization Command Word 1" type(icw1); 127 register slave_ocw2 wo also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 2" type(ocw2); 128 register slave_ocw3 wo also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 3" type(ocw3); 129 register slave_ocw3rd ro also io( base, 0xa0 ) "Slave PIC Op Ctrl Word 3" type(uint8); 130 131 register slave_icw2 wo io( base, 0xa1 ) "Slave PIC Initialization Command Word 2" type(icw2); 132 register slave_icw3 wo also io( base, 0xa1 ) "Slave PIC Initialization Command Word 3" type(pic_slave_icw3); 133 register slave_icw4 wo also io( base, 0xa1 ) "Slave PIC Initialization Command Word 4" type(icw4); 134 register slave_ocw1 rw also io( base, 0xa1 ) "Slave PIC Operation Control Word 1" type(uint8); 135 136 register master_trigger rw io( base, 0x4d0 ) "Master PIC Edge/Level Triggered" type(pic_master_trigger); 137 register slave_trigger rw io( base, 0x4d1 ) "Slave PIC Edge/Level Triggered" type(pic_slave_trigger); 138}; 139