1/* 2 * Copyright (c) 2007, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * lpc.dev 11 * 12 * DESCRIPTION: Definition of the PCI config space for the LPC (low 13 * pin count, or legacy PC) bridge function of a typical 14 * Intel IHC (Southbridge). 15 * 16 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub 17 * Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)". 18 * Other parts of this chapter have been broken out into other 19 * sections, because frankly, they're huge. 20 * 21 */ 22 23device LPC_pci ( addr conf ) "LPC IHC function" { 24 25 // 26 // This is big. First: 27 // Section 21.1: PCI configuration space. 28 // 29 30 register vid ro addr(conf, 0x00) "Vendor ID" type(uint16); 31 register did ro addr(conf, 0x02) "Device ID" { 32 fdcomp 4 "FDCOMP fuse"; 33 id 12 always(0x267) "device id"; 34 }; 35 36 register pcicmd addr(conf, 0x04) "PCI command" { 37 iose 1 ro "I/O space enable"; 38 mse 1 ro "Memory space enable"; 39 bme 1 ro "Bus master enable"; 40 sce 1 ro always(0) "Special cycle enable"; 41 mwie 1 ro always(0) "Memory write and invalidate enable"; 42 vps 1 ro always(0) "VGA palette snoop"; 43 pere 1 rw "Parity error response enable"; 44 wcc 1 ro always(0) "Wait cycle control"; 45 serr_en 1 rw "SERR# enable"; 46 fbe 1 ro always(0) "Fast back-to-back enable"; 47 _ 6 rsvd; 48 }; 49 50 register pcists addr(conf, 0x06) "PCI status" { 51 _ 3 rsvd; 52 is 1 ro "Interrupt status"; 53 clist 1 ro "Capabilities list"; 54 c66mhz 1 rsvd "66 Mhz capable"; 55 _ 1 rsvd; 56 fbc 1 rsvd "Fast back-to-back capable"; 57 dped 1 rwc "Data parity error detected"; 58 dev_sts 2 ro "DEVSEL# timing status"; 59 sta 1 rwc "Signalled target abort"; 60 rta 1 rwc "Received target abort"; 61 rma 1 rwc "Master abort status"; 62 sse 1 rwc "Signalled system error"; 63 dpe 1 rwc "Detected parity error"; 64 }; 65 66 register rid rwo addr(conf, 0x08) "Revision id" type(uint8); 67 register pi ro addr(conf, 0x09) "Programming interface" type(uint8); 68 register scc ro addr(conf, 0x0a) "Sub class code" type(uint8); 69 register bcc ro addr(conf, 0x0b) "Base class code" type(uint8); 70 register plt ro addr(conf, 0x0d) "Primary latency timer" type(uint8); 71 register headtyp ro addr(conf, 0x0e) "Header type" type(uint8); 72 73 register ss rwo addr(conf, 0x2c) "Subsystem identifiers" { 74 ssvid 16 rwo "Subsystem vendor id"; 75 ssid 16 rwo "Subsystem id"; 76 }; 77 78 register pmbase addr(conf, 0x40) "ACPI base address" { 79 rte 1 ro always(1) "Resource type indicator"; 80 _ 6 rsvd; 81 base 9 rw "Base address"; 82 _ 16 rsvd; 83 }; 84 85 constants sci_irq "SCI IRQ select map" { 86 irq9 = 0b000; 87 irq10 = 0b001; 88 irq11 = 0b010; 89 irq20 = 0b100; 90 irq21 = 0b101; 91 irq22 = 0b110; 92 irq23 = 0b111; 93 }; 94 95 register acpi_cntl addr(conf, 0x44) "ACPI control" { 96 sci_irq_sel 3 rw type(sci_irq) "SCI IRQ select"; 97 _ 4 rsvd; 98 acpi_en 1 rw "ACPI enable"; 99 }; 100 101 register gpiobase addr(conf, 0x48) "GPIO base address" { 102 _ 1 ro always(1); 103 _ 5 mbz; 104 ba 10 rw "Base address"; 105 _ 16 mbz; 106 }; 107 108 register gc addr(conf, 0x4c) "GPIO control" { 109 _ 4 rsvd; 110 en 1 rw "GPIO enable"; 111 _ 3 rsvd; 112 }; 113 114 regtype pirq_rout "PIRQ routing" { 115 routing 4 rw "IRQ routing"; 116 _ 3 rsvd; 117 irqen 1 rw "Interrupt routing enable"; 118 }; 119 register pirqa_rout addr(conf, 0x60) type(pirq_rout) "PIRQA routing control"; 120 register pirqb_rout addr(conf, 0x61) type(pirq_rout) "PIRQB routing control"; 121 register pirqc_rout addr(conf, 0x62) type(pirq_rout) "PIRQC routing control"; 122 register pirqd_rout addr(conf, 0x63) type(pirq_rout) "PIRQD routing control"; 123 register pirqe_rout addr(conf, 0x68) type(pirq_rout) "PIRQE routing control"; 124 register pirqf_rout addr(conf, 0x69) type(pirq_rout) "PIRQF routing control"; 125 register pirqg_rout addr(conf, 0x6A) type(pirq_rout) "PIRQG routing control"; 126 register pirqh_rout addr(conf, 0x6B) type(pirq_rout) "PIRQH routing control"; 127 128 register sirq_cntl addr(conf, 0x64) "Serial IRQ control" { 129 sfpw 2 rw "Start frame pulse width"; 130 sirqsz 4 ro "Serial IRQ frame size"; 131 sirqmd 1 rw "Serial IRQ mode select"; 132 sirqen 1 rw "Serial IRQ enable"; 133 }; 134 135 register lpc_iodec addr(conf, 0x80) "I/O decode ranges" { 136 coma 3 rw "COMA decode"; 137 _ 1 rsvd; 138 comb 3 rw "COMB decode"; 139 _ 1 rsvd; 140 lpt 2 rw "LPT decode"; 141 _ 2 rsvd; 142 fdd 1 rw "FDD decode"; 143 _ 3 rsvd; 144 }; 145 146 register lpc_en addr(conf, 0x82) "LPC i/f enables" { 147 coma 1 rw "Com port A"; 148 comb 1 rw "Com port B"; 149 lpt 1 rw "Parallel port"; 150 fdd 1 rw "Floppy"; 151 _ 4 rsvd; 152 gamel 1 rw "Low gameport"; 153 gameh 1 rw "High gameport"; 154 kbd 1 rw "Keyboard"; 155 mc 1 rw "Microcontroller"; 156 cnf1 1 rw "Super I/O"; 157 cnf2 1 rw "Microcontroller #2"; 158 _ 2 rsvd; 159 }; 160 161 register gen1_dec addr(conf, 0x84) "Generic decode range 1" { 162 en 1 rw "Enable"; 163 _ 6 rsvd; 164 base 9 rw "Base address"; 165 }; 166 167 register gen2_dec addr(conf, 0x88) "Generic decode range 2" { 168 en 1 rw "Enable"; 169 _ 3 rsvd; 170 base 12 rw "Base address"; 171 }; 172 173 register fwh_sel1 addr(conf, 0xd0) "Firmware hub select 1" { 174 idsel_c0 4 rw "IDSEL for ffc00000 & ff800000"; 175 idsel_c8 4 rw "IDSEL for ffc80000 & ff880000"; 176 idsel_d0 4 rw "IDSEL for ffd00000 & ff900000"; 177 idsel_d8 4 rw "IDSEL for ffd80000 & ff980000"; 178 idsel_e0 4 rw "IDSEL for ffe00000 & ffa00000"; 179 idsel_e8 4 rw "IDSEL for ffe80000 & ffa80000"; 180 idsel_f0 4 rw "IDSEL for fff00000 & ffb00000"; 181 idsel_f8 4 ro "IDSEL for fff80000 & ffb80000"; 182 }; 183 184 register fwh_sel2 addr(conf, 0xd4) "Firmware hub select 2" { 185 idsel_40 4 rw "IDSEL for ff400000 & ff000000"; 186 idsel_50 4 rw "IDSEL for ff500000 & ff100000"; 187 idsel_60 4 rw "IDSEL for ff600000 & ff200000"; 188 idsel_70 4 rw "IDSEL for ff700000 & ff300000"; 189 } 190 191 register fwh_dec_en1 addr(conf, 0xd8) "Firmware hub decode enable" { 192 en_40 1 rw "enable for ff400000 & ff000000"; 193 en_50 1 rw "enable for ff500000 & ff100000"; 194 en_60 1 rw "enable for ff600000 & ff200000"; 195 en_70 1 rw "enable for ff700000 & ff300000"; 196 _ 2 rsvd; 197 en_leg_e 1 rw "enable legacy e0000"; 198 en_leg_f 1 rw "enable legacy f0000"; 199 en_c0 1 rw "enable for ffc00000 & ff800000"; 200 en_c8 1 rw "enable for ffc80000 & ff880000"; 201 en_d0 1 rw "enable for ffd00000 & ff900000"; 202 en_d8 1 rw "enable for ffd80000 & ff980000"; 203 en_e0 1 rw "enable for ffe00000 & ffa00000"; 204 en_e8 1 rw "enable for ffe80000 & ffa80000"; 205 en_f0 1 rw "enable for fff00000 & ffb00000"; 206 en_f8 1 ro "enable for fff80000 & ffb80000"; 207 }; 208 209 register bios_cntl addr(conf, 0xdc) "BIOS control" { 210 bioswe 1 rw "BIOS write enable"; 211 ble 1 rw "BIOS lock enable"; 212 _ 6 rsvd; 213 }; 214 215 register rcba addr(conf, 0xf0) "Root complex base address" { 216 en 1 rw "Enable"; 217 _ 13 rsvd; 218 ba 18 rw "Base address"; 219 }; 220}; 221 222