1/*
2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * lpc_ioapic.dev
11 *
12 * DESCRIPTION: Definition of the LPC (low pin count, or legacy PC)
13 *              bridge function of a typical Intel IHC (Southbridge).
14 * 
15 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub
16 * Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)". 
17 */
18
19device lpc_ioapic lsbfirst (addr base) "LPC IHC I/O APIC function" {
20  //
21  // Advanced Programmable Interrupt Controller registers: section 21.5
22  //
23
24    space ioapic(index) stepwise(4) "I/O APIC register space";
25
26  constants delivery_mode "Delivery Mode" {
27    fixed   = 0b000	  "Fixed";
28    lowest  = 0b001	  "Lowest Priority";
29    smi	    = 0b010	  "SMI (System Management Interrupt)";
30    nmi	    = 0b100	  "NMI (Non-maskable Interrupt)";
31    init    = 0b101	  "INIT";
32    extint  = 0b111	  "ExtINT";
33  };
34
35  constants dest_mode "Destination Mode" {
36    physical	      = 0b0	   "Physical";
37    logical	      = 0b1	   "Logical";
38  };
39
40  constants delivery_status "Delivery Status" {
41    idle    = 0b0	    "Idle";
42    pending = 0b1	    "Pending";
43  };
44
45  constants polarity "Interrupt Input Pin Polarity" {
46    active_high	     = 0b0	"Active high";
47    active_low	     = 0b1	"Active low";
48  };
49
50  constants trigger_mode "Trigger Mode" {
51    edge    = 0b0	 "Edge Triggered";
52    level   = 0b1	 "Level Triggered";
53  };
54
55  register ind rw addr(base, 0x0) "Index" type(uint32);
56  register wdw rw addr(base, 0x10) "Window" type(uint32);
57
58  register eoir wo addr(base, 0x40) "EOI" {
59    rec	   8	"Redirection Entry Clear";
60    _	   24	mbz;
61  };
62
63  register id rw ioapic(0x0) "Identification" {
64    _	   15;
65    spb	   1	"Scratchpad bit";
66    _	   8;
67    id     4	"APIC ID";
68    _	   4;
69  };
70
71  register ver ro ioapic(0x1) "Version" {
72    ver	   8   	"Version";
73    _	   7;
74    prq	   1	"Pin assertion register non-support";
75    mre	   8	"Maximum redirection entries";
76    _	   8;
77  };
78
79  register arb ro ioapic(0x2) "Arbitration" {
80      _      24;
81      id     4   "IOAPIC Arbitration ID";
82      _	     4;
83  };
84
85
86  regtype redir_tbl "Redirection Table" {
87    vector 		 8	"Vector";
88    mode   		 3	type(delivery_mode) "Delivery mode";
89    destmode		 1	type(dest_mode) "Destination mode";
90    status 		 1	ro type(delivery_status) "Delivery status";
91    polarity		 1	type(polarity) "Interrupt input pin polarity";
92    rirr		 1	ro "Remote IRR";
93    trigger		 1	type(trigger_mode) "Trigger mode";
94    mask		 1	"Mask";
95    _			 31;
96    edid   		 8	ro "Extended destination ID";
97    dest   		 8	"Destination";
98  };
99
100  // XXX: Support up to 24 redirection table entries.
101  regarray redirtbl rw ioapic(0x10)[24] type(redir_tbl);
102};
103