1/* 2 * Copyright (c) 2007, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * lpc_dma.dev 11 * 12 * DESCRIPTION: Legacy DMA controllers on the LPC (low pin count, or 13 * legacy PC) bridge function of a typical Intel IHC 14 * (Southbridge). 15 * 16 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub 17 * Datasheet", chapter 21, "LPC Interface Bridge Registers (D31:F0)". 18 * 19 */ 20 21device LPC_dma ( io base ) "LPC DMA registers" { 22 23 // 24 // Section 21.2: DMA I/O registers 25 // 26 27 // Yuck. There's a baroque protocol for accessing these 28 // registers, which I'm not even going to attempt to express yet. 29 30 register base_a0 wo io(base, 0x00 ) "ch0 base addr" type(uint8); 31 register base_a1 wo io(base, 0x02 ) "ch1 base addr" type(uint8); 32 register base_a2 wo io(base, 0x04 ) "ch2 base addr" type(uint8); 33 register base_a3 wo io(base, 0x06 ) "ch3 base addr" type(uint8); 34 register base_a5 wo io(base, 0xc4 ) "ch5 base addr" type(uint8); 35 register base_a6 wo io(base, 0xc8 ) "ch6 base addr" type(uint8); 36 register base_a7 wo io(base, 0xcc ) "ch7 base addr" type(uint8); 37 38 register cur_a0 ro also io(base, 0x00 ) "ch0 cur addr" type(uint8); 39 register cur_a1 ro also io(base, 0x02 ) "ch1 cur addr" type(uint8); 40 register cur_a2 ro also io(base, 0x04 ) "ch2 cur addr" type(uint8); 41 register cur_a3 ro also io(base, 0x06 ) "ch3 cur addr" type(uint8); 42 register cur_a5 ro also io(base, 0xc4 ) "ch5 cur addr" type(uint8); 43 register cur_a6 ro also io(base, 0xc8 ) "ch6 cur addr" type(uint8); 44 register cur_a7 ro also io(base, 0xcc ) "ch7 cur addr" type(uint8); 45 46 register base_c0 wo also io(base, 0x00 ) "ch0 base count" type(uint8); 47 register base_c1 wo also io(base, 0x02 ) "ch1 base count" type(uint8); 48 register base_c2 wo also io(base, 0x04 ) "ch2 base count" type(uint8); 49 register base_c3 wo also io(base, 0x06 ) "ch3 base count" type(uint8); 50 register base_c5 wo also io(base, 0xc4 ) "ch5 base count" type(uint8); 51 register base_c6 wo also io(base, 0xc8 ) "ch6 base count" type(uint8); 52 register base_c7 wo also io(base, 0xcc ) "ch7 base count" type(uint8); 53 54 register cur_c0 ro also io(base, 0x00 ) "ch0 cur count" type(uint8); 55 register cur_c1 ro also io(base, 0x02 ) "ch1 cur count" type(uint8); 56 register cur_c2 ro also io(base, 0x04 ) "ch2 cur count" type(uint8); 57 register cur_c3 ro also io(base, 0x06 ) "ch3 cur count" type(uint8); 58 register cur_c5 ro also io(base, 0xc4 ) "ch5 cur count" type(uint8); 59 register cur_c6 ro also io(base, 0xc8 ) "ch6 cur count" type(uint8); 60 register cur_c7 ro also io(base, 0xcc ) "ch7 cur count" type(uint8); 61 62 register mem_lp0 rw io(base, 0x87 ) "ch0 mem low page" type(uint8); 63 register mem_lp1 rw io(base, 0x83 ) "ch1 mem low page" type(uint8); 64 register mem_lp2 rw io(base, 0x81 ) "ch2 mem low page" type(uint8); 65 register mem_lp3 rw io(base, 0x82 ) "ch3 mem low page" type(uint8); 66 register mem_lp5 rw io(base, 0x8b ) "ch5 mem low page" type(uint8); 67 register mem_lp6 rw io(base, 0x89 ) "ch6 mem low page" type(uint8); 68 register mem_lp7 rw io(base, 0x8a ) "ch7 mem low page" type(uint8); 69 70 regtype dmacmd "DMA command" { 71 _ 2 mbz; 72 chgrp_en 1 "channel group enable"; 73 _ 1 mbz; 74 grp_arb 1 "group arbitration priority"; 75 _ 3 mbz; 76 }; 77 register dmacmd_03 wo io(base, 0x08 ) "DMA cmd ch0-3" type(dmacmd); 78 register dmacmd_47 wo io(base, 0xd0 ) "DMA cmd ch4-7" type(dmacmd); 79 80 regtype dmasta "DMA status" { 81 ch_tcs 4 "Channel terminal count status"; 82 ch_reqs 4 "Channel request status"; 83 }; 84 register dmasta_03 ro also io(base, 0x08 ) "DMA status ch0-3" type(dmasta); 85 register dmasta_47 ro also io(base, 0xd0 ) "DMA status ch4-7" type(dmasta); 86 87 regtype dma_wrsmsk "DMA write single mask" { 88 ch_sel 2 "channel select"; 89 mask 1 "Channel mask select"; 90 _ 5 mbz; 91 }; 92 register dma_wrsmsk_03 wo io(base, 0x0a ) "DMA wrt single msk ch0-3" type(dma_wrsmsk); 93 register dma_wrsmsk_47 wo io(base, 0xd4 ) "DMA wrt single msk ch4-7" type(dma_wrsmsk); 94 95 constants dma_trans_type "DMA transaction type" { 96 verify = 0b00; 97 write = 0b01; 98 read = 0b10; 99 illegal = 0b11; 100 }; 101 constants dma_trans_mode "DMA transaction mode" { 102 demand = 0b00; 103 single = 0b01; 104 cascade = 0b11; 105 }; 106 107 regtype dmach_mode "channel mode" { 108 ch_sel 2 "channel select"; 109 trans_tp 2 type(dma_trans_type) "transfer type"; 110 auto_init 1 "Autoinitialize enable"; 111 inc_dec 1 "Address inc/dec select"; 112 trans_mode 2 type(dma_trans_mode) "transfer mode"; 113 }; 114 115 register dmach_mode_03 wo io(base, 0x0b ) "chan mode ch0-3" type(dmach_mode); 116 register dmach_mode_47 wo io(base, 0xd6 ) "chan mode ch4-7" type(dmach_mode); 117 118 register dma_clbp_03 wo io(base, 0x0c ) "clr byte ptr ch0-3" type(uint8); 119 register dma_clbp_47 wo io(base, 0xd8 ) "clr byte ptr ch4-7" type(uint8); 120 121 register dma_mclr_03 wo io(base, 0x0d ) "master clr ch0-3" type(uint8); 122 register dma_mclr_47 wo io(base, 0xda ) "master clr ch4-7" type(uint8); 123 124 register dma_clrmsk_03 wo io(base, 0x0e ) "clr mask ch0-3" type(uint8); 125 register dma_clrmsk_47 wo io(base, 0xdc ) "clr mask ch4-7" type(uint8); 126 127 regtype dma_wrmsk "write all mask" { 128 chan 4 "Channel mask bits"; 129 _ 4 mbz; 130 }; 131 register dma_wrmsk_03 rw io(base, 0x0f ) "write all mask ch0-3" type(dma_wrmsk); 132 register dma_wrmsk_47 rw io(base, 0xde ) "write all mask ch4-7" type(dma_wrmsk); 133 134}; 135 136