1/*
2 * Copyright (c) 2007, 2008, 2009, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * netronome_uart.dev
11 *
12 * DESCRIPTION: Netronome Universal Asynchronous Receiver Transmitter
13 *              similar to 16550 UART
14 *
15 * This is derived from the Intel IXP2400/IXP2800 Network Processor 
16 * Programmer's Reference Manual (November 2003), p. 364ff
17 */
18
19device ixp2800_uart msbfirst ( addr base ) "Netronome UART Memory Represenation" {
20
21
22
23/* Bram: I cannot verify this, maybe p.365 gives hints? */
24/* ******************************************************/
25
26  constants divisor "Baud Rate Divisor" {
27    baud50          = 2304     "50 bps";
28    baud75          = 1536     "75 bps";
29    baud110         = 1047     "110 bps";
30    baud134_5       = 857      "134.5 bps";
31    baud150         = 768      "150 bps";
32    baud300         = 384      "300 bps";
33    baud600         = 192      "600 bps";
34    baud1200        = 96       "1200 bps";
35    baud1800        = 64       "1800 bps";
36    baud2000        = 58       "2000 bps";
37    baud2400        = 48       "2400 bps";
38    baud4800        = 24       "4800 bps";
39    baud7200        = 16       "7200 bps";
40    baud9600        = 12       "9600 bps";
41    baud19200       = 6        "19200 bps";
42    baud38400       = 3        "38400 bps";
43    baud57600       = 2        "57600 bps";
44    baud115200      = 1        "115200 bps";
45  };
46
47  constants interrupt_source "Interrupt Source Encoded" {
48    request_data   = 0b01   "Transmit FIFO requests data";
49    recv_data_av   = 0b10   "Received Data Available";
50    recv_error	   = 0b11   "Receive error";
51   };
52
53  constants fifo_type "FIFO Mode Enable Status" {
54    no_fifo         = 0b00      "No FIFO";
55    fifo_enabled    = 0b11      "FIFO enabled";
56  };
57
58  constants interrupt_trigger "Interrupt Trigger Level" {
59    bytes01  = 0b00   "1  byte in FIFO causes interrupt";
60    bytes08  = 0b01   "8  byte in FIFO causes interrupt";
61    bytes16  = 0b10   "16 byte in FIFO causes interrupt";
62    bytes32  = 0b11   "32 byte in FIFO causes interrupt";
63  };
64
65  constants char_len "Character Length" {
66    bits5   = 0b00   "5 Bits";
67    bits6   = 0b01   "6 Bits";
68    bits7   = 0b10   "7 Bits";
69    bits8   = 0b11   "8 Bits";
70  };
71
72  register RBR ro addr ( base, 0x0 ) "Receiver buffer" {
73    _	       	  24 ro "Reserved";
74    rbr		  8  ro "Receive Buffer Register. Data byte received, least significant bit first";
75  };
76
77  register THR also addr ( base , 0x0 ) "Transmitter holding" {
78    _	       	  24 ro "Reserved";
79    thr		  8  wo "Data byte transmitted, least significant bit first";
80  };
81
82  register DLRL also addr (base , 0x0) "Divisor Latch low" {
83    _	       	  24 ro "Reserved";
84    lb		  8  rw "Low byte for generating baud rate";
85  };
86  
87  register DLRH addr (base , 0x4) "Divisor Latch high" {
88    _	       	  24 ro "Reserved";
89    hb		  8  rw "High byte for generating baud rate";
90  };
91    
92  register IER also addr ( base, 0x4 ) "Interrupt enable" {
93    _	       	  25 ro	"Reserved";
94    uue		  1  rw "UART Unit Enable";
95    nrze	  1  rw "NRZ coding Enable";
96    rtoie	  1  rw	"Receiver Time out Interrupt Enable";
97    _		  1  rw	"Reserved";
98    rlse	  1  rw	"Receiver Line Status Interrupt Enable";
99    tie		  1  rw	"Transmit Data request Interrupt Enable";
100    ravie	  1  rw	"Receiver Data Available Interrupt Enable";
101  };
102
103  register iir addr ( base, 0x8 ) "Interrupt identification" {
104    _	       	 24 ro "Reserved";
105    FIFOES	 2  ro type(fifo_type) "FIFO Mode Enable Status"; 
106    _		 2  ro "Reserved";
107    TOD		 1  ro "Time Out Detected (0: No time out interrupt is pending)";
108    IID		 2  ro type(interrupt_source) "Interrupt Source Encoded";
109    IP		 1  ro "Interrupt Pending";
110  };
111
112  register fcr rw also addr ( base, 0x8 ) "FIFO control" {
113    _	         24 ro "Reserved";
114    ITL 	 2  wo type(interrupt_trigger) "Interrupt Trigger Level";
115    _		 3  ro "Reserved";
116    RESETTF 	 1  wo "Reset transmitter FIFO";
117    RESETRF 	 1  wo "Reset Receiver FIFO";
118    TRFIFOE 	 1  wo "Transmit and Receive FIFO Enable";
119  };
120
121  register LCR addr ( base, 0xC ) "Line control" {
122    _	       	  24 ro "Reserved";
123    dlab          1  rw "Divisor latch access";
124    sb            1  rw "Set break";
125    stkyp         1  rw "Stick parity";
126    eps           1  rw "Even parity select";
127    pen           1  rw "Parity enable";
128    stb           1  rw "Number of stop bits";
129    wls           2  rw type(char_len) "Word length select";
130  };
131
132  register LSR addr ( base, 0x14 ) "Line status" {
133    _	          24 ro "Reserved";
134    fifoe         1  ro "FIFO Error Status ";
135    temt          1  ro "Transmitter empty";
136    tdrq	  1  ro	"Transmit Data Request";
137    bi            1  ro "Break interrupt";
138    fe            1  ro "Framing error";
139    pe            1  ro "Parity error";
140    oe            1  ro "Overrun error";
141    dr            1  ro "Data ready";
142  };
143
144
145  register spr addr ( base, 0x1c ) "Scratchpad register" {
146    _	       	  24 ro "Reserved";
147    scratch	  8  rw	"No effect on UART functionality";
148  };
149
150};
151