1/*
2 * Copyright (c) 2009, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * arm_icp_pit.dev
11 *
12 * DESCRIPTION: Timers for for integrator/cp
13 *
14 * This is derived from:
15 *
16 * This is derived from the Intel IXP2400/IXP2800 Network Processor 
17 * Programmer's Reference Manual (November 2003), p. 352ff
18 *
19 */
20
21device ixp2800_icp_pit msbfirst ( addr base ) "IXP2800 Integrator timer"
22{
23  // p.352, section 5.6.5.1 
24  constants scale "Timer scaling factors" {
25    none   = 0b00 "Use clock to trigger counter";
26    div16  = 0b01 "Use clock devided by 16 to trigger counter";
27    div256 = 0b10 "Use clock devided by 256 to trigger counter";
28    gpio   = 0b11 "Use GPIO pins";
29  };
30
31
32  register CONTROL addr(base, 0x00) "Control register" {
33    _         24   ro "Reserved";
34    ACT        1   rw "Activate timer";
35    _          3   ro "Reserved";
36    PSS	       2   rw type(scale) "Select the pre-scalar";
37    _          2   ro "Reserved";
38  };
39
40  register LOADING addr(base, 0x10) "Load value for timer" {
41    CLV      32   rw "Counter initial value";
42  };
43
44  register STATUS addr(base, 0x20) "Current value for timer" {
45    CSV      32   rw "Current counter value";
46  };
47
48  register CLEAR addr(base, 0x30) "Interrupt clear" {
49    _	     31	  ro "Reserved";
50    ICL       1   rw "Write one to clear interrupt";
51  };
52
53  register WATCHDOG addr(base, 0x40) "Enable timer 4 to be a watchdog timer" {
54    _	     31   ro "Reserved";
55    WDE	      1	  rw "Write one to enable watchdog";
56  }; 
57
58};
59
60