1/* 2 * Copyright (c) 2019, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * sdhc.dev 11 * 12 * DESCRIPTION: IMX8X SD Host Controller 13 * 14 * See: 15 * SD Specifications Part A2: SD Host Controller Simplified Specification 16 * Version 3.00, February 25, 2011. 17 * Technical Committee, SD Association 18 * 19 */ 20 21 device sdhc msbfirst (addr base) "IMX8X SD Host Controller" { 22 23 // 14.8.8.1.2 24 register ds_addr rw addr(base, 0x00) "DMA system address" type(uint32); 25 register cmd_arg2 rw also addr(base, 0x00) "Argument 2" type(uint32); 26 27 // 14.8.8.1.3 28 register blk_att rw addr(base, 0x04) "Block count" { 29 blkcnt 16 "Block count"; 30 _ 3 mbz; 31 blksize 13 "Transfer block size (bytes)"; 32 }; 33 34 // 14.8.8.1.4 35 register cmd_arg rw addr(base, 0x08) "Argument 1" type(uint32); 36 37 // 14.8.8.1.5 38 constants auto_en "Auto command enable values" { 39 auto_en_dis = 0b00 "Auto Command Disabled"; 40 auto_en_12 = 0b01 "Auto CMD12 Enable"; 41 auto_en_23 = 0b10 "Auto CMD23 Enable"; 42 }; 43 constants cmd_tp "Command type" { 44 cmd_tp_abrt = 0b11 "Abort CMD12, CMD52 for writing I/O Abort"; 45 cmd_tp_rsme = 0b10 "Resume CMD52 for writing Function Select"; 46 cmd_tp_susp = 0b01 "Suspend CMD52 for writing Bus Suspend"; 47 cmd_tp_norm = 0b00 "Normal; other commands"; 48 }; 49 constants rsp_tp "Response type" { 50 rsp_tp_none = 0b00 "No response"; 51 rsp_tp_136 = 0b01 "Response length 136"; 52 rsp_tp_48 = 0b10 "Response length 48"; 53 rsp_tp_48cb = 0b11 "Response length 48 check busy after response"; 54 }; 55 register cmd_xfr_typ rw addr(base, 0x0C) "Command Transfer Type" { 56 _ 2 mbz; 57 cmdinx 6 "Command index"; 58 cmdtyp 2 type(cmd_tp) "Command type"; 59 dpsel 1 "Data present select"; 60 cicen 1 "Command index check enable"; 61 cccen 1 "Command CRC check enable"; 62 _ 1 mbz; 63 rsptyp 2 type(rsp_tp) "Response type select"; 64 _ 16 mbz; 65 }; 66 67 // 14.8.8.1.6-9 68 register cmd_rsp0 rw addr(base, 0x10) "Command Response 0" type(uint32); 69 register cmd_rsp1 rw addr(base, 0x14) "Command Response 1" type(uint32); 70 register cmd_rsp2 rw addr(base, 0x18) "Command Response 2" type(uint32); 71 register cmd_rsp3 rw addr(base, 0x1C) "Command Response 3" type(uint32); 72 73 // 14.8.8.1.10 74 register data_buff_acc_port rw addr(base, 0x20) "Data Buffer Access Port" type(uint32); 75 76 77 // 14.8.8.1.11 78 register pres_state rw addr(base, 0x24) "Present State" { 79 dlsl 8 "Data Line Signal Level"; 80 clsl 1 "CMD Line Signal Level"; 81 _ 3 mbz; 82 wpspl 1 "Write Protect Switch Pin Level"; 83 cdpl 1 "Card Detect Pin Level"; 84 _ 1 mbz; 85 cinst 1 "Card inserted"; 86 tscd 1 "Tape Select Change Done"; 87 _ 2 mbz; 88 rtr 1 "Retuning request"; 89 bren 1 "Buffer read enable"; 90 bwen 1 "Buffer write enable"; 91 rta 1 "Read transfer active"; 92 wta 1 "Write transfer active"; 93 sdoff 1 "SD Clock Gated Off Internally"; 94 peroff 1 "IPG_PERCLK Gated Off Internally"; 95 hckoff 1 "HCLK Gated Off Internally"; 96 ipgoff 1 "IPG_CLK Gated Off Internally"; 97 sdstb 1 "SD Clock Stable"; 98 dla 1 "Data Line Active"; 99 cdihb 1 "Command Inhibit (DATA)"; 100 cihb 1 "Command Inhibit (CMD)"; 101 }; 102 103 // 14.8.8.1.12 104 register prot_ctrl rw addr(base, 0x28) "Protocol Control" { 105 _ 1 mbz; 106 non_exact_blk_rd 1; 107 _ 3 mbz; 108 wecrm 1; 109 wecins 1; 110 wecint 1; 111 _ 3; 112 rd_done_no_8clk 1; 113 iabg 1; 114 rwctl 1; 115 creq 1; 116 sabgreq 1; 117 _ 6 mbz; 118 dmasel 2; 119 cdss 1; 120 cdtl 1; 121 emode 2; 122 d3cd 1; 123 dtw 2; 124 lctl 1; 125 }; 126 127 // 14.8.8.1.13 128 register sys_ctrl rw addr(base, 0x2C) "System control" { 129 _ 3 mbz; 130 rstt 1 "Reset Tuning"; 131 inita 1 "initialization activation"; 132 rstd 1 "Software reset Data"; 133 rstc 1 "Software reset CMD"; 134 rsta 1 "Software reset ALL"; 135 ipp_rst_n 1 ""; 136 _ 3 mbz; 137 dtocv 4 "data timeout counter value"; 138 sdclkfs 8 "sdclk frequency select"; 139 dvs 4 "divisor"; 140 _ 4 mbz; 141 142 }; 143 144 // 14.8.8.1.14 145 register int_status rw1c addr(base, 0x30) "Inerrupt Status" { 146 _ 3 mbz; 147 dmae 1 "DMA Error"; 148 _ 1 mbz; 149 tne 1 "Tuning Error"; 150 _ 1 mbz; 151 ac12e 1 "Auto Cmd 12 Error"; 152 _ 1 mbz; 153 debe 1 "Data End Bit Error"; 154 dce 1 "Data CRC Error"; 155 dtoe 1 "Data Timeout Error"; 156 cie 1 "Command Index Error"; 157 cebe 1 "Command End Bit error"; 158 cce 1 "Command CRC Error"; 159 ctoe 1 "Command Timeout Error"; 160 161 // 16 bit boundary 162 _ 1 mbz; 163 cqi 1 "Command Queueing Interrupt"; 164 tp 1 "Tuning pass"; 165 rte 1 "Re-Tuning event"; 166 _ 3 mbz; 167 cint 1 "Card interrupt"; 168 crm 1 "Card removal"; 169 cins 1 "Card insertion"; 170 brr 1 "Buffer read ready"; 171 bwr 1 "Buffer write ready"; 172 dint 1 "DMA interrupt"; 173 bge 1 "Block gap event"; 174 tc 1 "Transfer complete"; 175 cc 1 "Command complete"; 176 }; 177 178 regtype ir "Interrupt Enable Register" { 179 _ 3 mbz; 180 dmaeen 1 "DMA Error"; 181 _ 1 mbz; 182 tneen 1 "Tuning Error"; 183 _ 1 mbz; 184 ac12een 1 "Auto Cmd 12 Error"; 185 _ 1 mbz; 186 debeen 1 "Data End Bit Error"; 187 dceen 1 "Data CRC Error"; 188 dtoeen 1 "Data Timeout Error"; 189 cieen 1 "Command Index Error"; 190 cebeen 1 "Command End Bit error"; 191 cceen 1 "Command CRC Error"; 192 ctoeen 1 "Command Timeout Error"; 193 194 // 16 bit boundary 195 _ 1 mbz; 196 cqien 1 "Command Queueing Interrupt"; 197 tpen 1 "Tuning pass"; 198 rteen 1 "Re-Tuning event"; 199 _ 3 mbz; 200 cinten 1 "Card interrupt"; 201 crmen 1 "Card removal"; 202 cinsen 1 "Card insertion"; 203 brren 1 "Buffer read ready"; 204 bwren 1 "Buffer write ready"; 205 dinten 1 "DMA interrupt"; 206 bgeen 1 "Block gap event"; 207 tcen 1 "Transfer complete"; 208 ccen 1 "Command complete"; 209 }; 210 211 register int_status_en addr(base, 0x34) "Interrupt Status enable" type(ir); 212 register int_signal_en addr(base, 0x38) "Interrupt Signal enable" type(ir); 213 214 // 14.8.8.1.17 215 register autocmd12_err_status addr(base, 0x3c) "Auto CMD12 Error Status" { 216 _ 8 mbz; 217 smp_clk_sel 1; 218 execute_tuning 1; 219 _ 14 mbz; 220 cnibac12e 1; 221 _ 2 mbz; 222 ac12ie 1; 223 ac12ce 1; 224 ac12ebe 1; 225 ac12toe 1; 226 ac12ne 1; 227 }; 228 229 // 14.8.8.1.18 230 register host_ctrl_cap addr(base, 0x40) "Host Controller Capabilities" { 231 _ 5 mbz; 232 vs_18 1; 233 vs_30 1; 234 vs_33 1; 235 srs 1; 236 dmas 1; 237 hss 1; 238 admas 1; 239 _ 1 mbz; 240 mbl 3; 241 retuning_mode 2; 242 use_tuning_sdr50 1; 243 _ 1 mbz; 244 time_count_retuning 4; 245 _ 5 mbz; 246 ddr50_support 1; 247 sdr104_support 1; 248 sdr50_support 1; 249 }; 250 251 // 14.8.8.1.19 252 register wtmk_lvl addr(base, 0x44) "Watermark Level" { 253 _ 8 mbz; 254 wr_wml 8; 255 _ 8 mbz; 256 rd_wml 8; 257 }; 258 259 // 14.8.8.1.20 260 register mix_ctrl addr(base, 0x48) "Mix Control" { 261 _ 1 mb1; 262 _ 1 mbz; 263 _ 1 mbz; 264 _ 1; 265 en_hs400_mode 1; 266 hs400_mode 1; 267 fbclk_sel 1; 268 auto_tune_en 1; 269 smp_clk_sel 1; 270 exe_tune 1; 271 _ 14; 272 ac23en 1; 273 nibble_pos 1; 274 msbsel 1; 275 dtdsel 1; 276 ddr_en 1; 277 ac12en 1; 278 bcen 1; 279 dmaen 1; 280 }; 281 282 // 14.8.8.1.24 283 register dll rw addr(base, 0x60) "Delay line control" { 284 dll_ctrl_ref_update_int 4; 285 dll_ctrl_slv_update_int 8; 286 _ 1 mbz; 287 dll_ctrl_slv_dly_target1 3; 288 dll_ctrl_slv_override_val 7; 289 dll_ctrl_slv_override 1; 290 dll_ctrl_gate_update 1; 291 dll_ctrl_slv_dly_target0 4; 292 dll_ctrl_slv_force_upd 1; 293 dll_ctrl_reset 1; 294 dll_ctrl_enable 1; 295 }; 296 297 // 14.8.8.1.26 298 register clk_tune_ctrl_status rw addr(base, 0x68) "CLK Tuning Control and Status" { 299 pre_err 1; 300 tap_sel_pre 7; 301 tap_sel_out 4; 302 tap_sel_post 4; 303 nxt_err 1; 304 dly_cell_set_pre 7; 305 dly_cell_set_out 4; 306 dly_cell_set_post 4; 307 }; 308 309 // 14.8.8.1.29 310 //register vend_spec rw addr(base, 0xC0) "Vendor Specific" { 311 // cmd_byte_en 1 "cmd byte en"; 312 // _ 15 mbz; 313 // crc_chk_dis 1 "CRC Check Disable"; 314 // _ 6 mbz; 315 // frc_sdclk_on 1 "Force CLK output active"; 316 // _ 4 mbz; 317 // ac12_wr_chkbusy_en 1 "Check busy enable"; 318 // conflict_chk_en 1 "Conflic check enable"; 319 // vselect 1 "Voltage selection"; 320 // _ 1 mbz; 321 //}; 322 323 // This is vend_spec according to uboot 324 register vend_spec rw addr(base, 0xC0) "Vendor Specific" { 325 _ 17 mbz; 326 cken 1; 327 peren 1; 328 hcken 1; 329 ipgen 1; 330 _ 11 mbz; 331 }; 332 333 334 // 14.8.8.1.30 335 register mmc_boot rw addr(base, 0xC4) "MMC Boot Register" { 336 boot_blk_cnt 16; 337 _ 7 mbz; 338 disable_time_out 1; 339 auto_sabg_en 1; 340 boot_en 1; 341 boot_mode 1; 342 boot_ack 1; 343 dtocv_ack 4; 344 }; 345 346 // 14.8.8.1.31 347 register vend_spec2 rw addr(base, 0xC8) "Vendor Specific 2" { 348 fbclk_tap_sel 16; 349 en_32k_clk 1; 350 bus_rst 1; 351 part_dll_debug 1; 352 acmd23_argu2_en 1; 353 hs400_rd_clk_stop_en 1; 354 hs400_wr_clk_stop_en 1; 355 _ 3 mbz; 356 tuning_cmd_en 1; 357 tuning_1bit_en 1; 358 tuning_8bit_en 1; 359 card_int_d3_test 1; 360 _ 3 mbz; 361 362 }; 363 364 365 366 }; 367