1/* 2 * Copyright (c) 2008, 2009, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * ht_config.dev 11 * 12 * DESCRIPTION: HyperTransport Configuration 13 * 14 * This is derived from the "BIOS and Kernel Developer's Guide (BKDG) 15 * for AMD Family 10h Processors", Chapter 3, "Registers". 16 */ 17 18device ht_config lsbfirst ( pci base ) "HyperTransport Configuration" { 19 // 20 // Section 3.3: Function 0 HyperTransport Technology Configuration 21 // Registers 22 // 23 24 constants rtdest "Routing Destination" { 25 self = 0b1 "Route to this node"; 26 link0_0 = 0b10 "Route to link 0, sublink 0"; 27 link1_0 = 0b100 "Route to link 1, sublink 0"; 28 link2_0 = 0b1000 "Route to link 2, sublink 0"; 29 link3_0 = 0b10000 "Route to link 3, sublink 0"; 30 link0_1 = 0b100000 "Route to link 0, sublink 1"; 31 link1_1 = 0b1000000 "Route to link 1, sublink 1"; 32 link2_1 = 0b10000000 "Route to link 2, sublink 1"; 33 link3_1 = 0b100000000 "Route to link 3, sublink 1"; 34 }; 35 36 regtype rtnode "Routing Table" { 37 rqrte 9 type(rtdest) "Request Route"; 38 rprte 9 type(rtdest) "Response Route"; 39 bcrte 9 type(rtdest) "Broadcast Route"; 40 _ 5; 41 }; 42 43 regarray rtnodes rw pci( base, 0x40 ) [8] "Routing Table Nodes" type(rtnode); 44 45 register nodeid rw pci( base, 0x60 ) "Node ID" { 46 nodeid 3 "This Node ID"; 47 _ 1; 48 nodecnt 3 "Node Count"; 49 _ 1; 50 sbnode 3 "HyperTransport I/O Hub Node ID"; 51 _ 1; 52 lknode 3 "Lock Controller Node ID"; 53 _ 1; 54 cpucnt 5 "CPU Count"; 55 _ 3 mbz; 56 _ 8; 57 }; 58 59 register unitid rw pci( base, 0x64 ) "Unit ID" { 60 cpuunit 2 "CPU Unit ID"; 61 _ 2; 62 mctunit 2 "Memory Controller Unit ID"; 63 hbunit 2 "Host Bridge Unit ID"; 64 sblink 3 "Southbridge I/O Hub Link ID"; 65 _ 21; 66 }; 67 68 // ... 69}; 70