1/* 2 * Copyright (c) 2007 - 2018, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * hpet.dev 11 * 12 * DESCRIPTION: Intel 631xESB/632xESB I/O Controller Hub -- 13 * High-Precision Event Timer Registers 14 * 15 * This is derived from the "Intel 631xESB/632xESB IO/Controller Hub 16 * Datasheet", chapter 26, "High-Precision Event Timer Registers". 17 * See also, Intel's "IA-PC HPET (High Precision Event Timers) 18 * Specification", Revision 1.0a, October 2004. 19 */ 20 21 // device device_name leastSignBitFirst 22device hpet lsbfirst ( addr base ) "High-Precision Event Timer" { 23 // 26.1.1 24 register gcap_id ro addr(base, 0x0) "General Capabilities and Identification" { 25 rev_id 8 "Revision Identification"; 26 num_tim_cap 5 "Number of Timers"; 27 count_size_cap 1 "Counter Size"; 28 _ 1 mbz; 29 leg_rt_cap 1 "Legacy Replacement Rout Capable"; 30 vendor_id_cap 16 "Vendor ID"; 31 counter_clk_per_cap 32 "Main Counter Tick Period"; 32 }; 33 34 // 26.1.2 register name attribute space(, ) "description" 35 36 register gen_conf rw addr(base, 0x10) "General Configuration" { 37 enable_cnf 1 "Overall Enable"; 38 leg_rt_cnf 1 "Legacy Replacement Rout"; 39 _ 62 mbz; 40 }; 41 42 // 26.1.3 43 register gintr_sta rw addr(base, 0x20) "General Interrupt Status" { 44 t00_int_sts 1 "Timer 0 interrupt active"; 45 t01_int_sts 1 "Timer 1 interrupt active"; 46 t02_int_sts 1 "Timer 2 interrupt active"; 47 _ 61 mbz; 48 }; 49 50 // 26.1.4 51 register main_cnt rw addr(base, 0xf0) "Main Counter Value" type(uint64); 52 53 // 26.1.5 54 regtype tim_conf "Timer Configuration and Capabilities" { 55 _ 1 mbz; 56 timer_int_type_cnf 1 "Timer Interrupt Type (0:edge-triggered , 1:level-triggered)"; 57 timer_int_enb_cnf 1 "Timer Interrupt Enable"; 58 timer_type_cnf 1 "Timer Type (0: non-periodic , 1:periodic)"; 59 timer_per_int_cap 1 "Periodic Interrupt Capability"; 60 timer_size_cap 1 "Timer Size (0:32 bits , 1:64 bits)"; 61 timer_val_set_cnf 1 "Timer Value Set (for periodic mode)"; 62 _ 1 mbz; 63 timer_32mode_cnf 1 "Timer 32-bit mode (1 so that 64 behaves as 32)"; 64 timer_int_rout_cnf 5 "Interrupt Route (indicates routing to I/O apic)"; 65 timer_fsb_enb_cnf 1 "FSB Interrupt Enable"; 66 timer_fsb_int_delv_cap 1 "FSB Interrupt Delivery (1: FSB is supported)"; 67 _ 16 mbz; 68 timer_int_rout_cap 32 "Interrupt Routing Capability (To which interrupts can the I/O Apic be routed)"; 69 }; 70 71 72 regtype tim_fsb_int_route "Timer FSB Interrupt Route"{ 73 timer_fsb_int_val 32 "Timer FSB Interrupt Value"; 74 timer_fsb_int_addr 32 "Timer FSB Interrupt Address"; 75 }; 76 77 regarray timers_config_reg rw addr(base,0x100) [32 ; 0x20] 78 "Timer N Configuration Register" type(tim_conf); 79 80 regarray timers_comparator_reg rw addr(base,0x108) [32 ; 0x20] 81 "Timer N Comparator Value Register" type(uint64); 82 83 regarray timers_fsb_int_route_reg rw addr(base,0x110) [32 ; 0x20] 84 "Timer N FSB Interrupt Route" type(tim_fsb_int_route); 85}; 86