1/*
2 * Copyright (c) 2018, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * gic_v3.dev
11 *
12 * DESCRIPTION: GIC v3 architecture definitions
13 *
14 * See:
15 *   GIC v3 Architecture Specification
16 */
17
18device gic_v3_redist msbfirst (addr redist) "GIC v3 Redistributor" {
19    register GICR_CTLR also addr(redist, 0x0000) "Redistributor Control Register" {
20        UWP         1   ro "Upstream Write Pending";
21        _           4   mbz;
22        DPG1S       1   "Disable Processor selection for Group 1 Secure interrupts";
23        DPG1NS      1   "Disable Processor selection for Group 1 Non-secure interrupts";
24        DPG0        1   "Disable Processor selection for Group 0 interrupts";
25        _           20  mbz;
26        RWP         1   "Register Write Pending";
27        _           2   mbz;
28        Enable_LPIs 1   "LPI support is enabled";
29    };
30
31    register GICR_IIDR ro addr(redist, 0x0004) "Redistributor Implementer Identification Register" {
32        ProductID   8   "Product identifier";
33        _           4   mbz;
34        Variant     4   "Variant number";
35        Revision    4   "Revision number";
36        Implementer 12  "JEP106 code of implementing company";
37    };
38
39    register GICR_TYPER ro addr(redist, 0x0008) "Redistributor Type Register" {
40        Affinity_Value  32  "The identity of the PE associated with this Redistributor";
41        _           6   mbz;
42        CommonLPIAff        2   "The affinity level at which Redistributors share a LPI Configuration table";
43        Processor_Number    16  "A unique identifier for the PE";
44        _           2   mbz;
45        DPGS        1   "Implementation supports LPIs";
46        Last        1   "Implementation supports LPIs";
47        DirectLPI   1   "Implementation supports LPIs";
48        _           1   mbz;
49        VLPIS       1   "Implementation supports LPIs";
50        PLPIS       1   "Implementation supports LPIs";
51    };
52
53    register GICR_STATUSR addr(redist, 0x0010) "Error Reporting Status Register" {
54        _       28  mbz;
55        WROD    1   "Write to RO location has been detected";
56        RWOD    1   "Read of WO location has been detected";
57        WRD     1   "Write to reserved location has been detected";
58        RRD     1   "Read to reserved location has been detected";
59    };
60
61    register GICR_WAKER addr(redist, 0x0014) "Redistributor Wake Register" {
62        IMP_DEF2        1   "Implementation Defined";
63        _               28  mbz;
64        ChildrenAsleep  1   ro "Indicates whether the connected PE is quiescent";
65        ProcessorSleep  1   "Indicates whether the Redistributor can assert the WakeRequest signal";
66        IMP_DEF1        1   "Implementation Defined";
67    };
68    
69    register GICR_IGROUPR0 addr(redist, 0x10080) "Interrupt Group Register 0" type(uint32);
70
71    register GICR_ISENABLER0 addr(redist, 0x10100) "Interrupt Set-Enable Register 0" type(uint32);
72
73    register GICR_ICENABLER0 addr(redist, 0x10180) "Interrupt Clear-Enable Register 0" type(uint32);
74
75    register GICR_ISPENDR0 addr(redist, 0x10200) "Interrupt Set-Pending Register 0" type(uint32);
76
77    register GICR_ICPENDR0 addr(redist, 0x10280) "Interrupt Clear-Pending Register 0" type(uint32);
78
79    register GICR_ISACTIVER0 addr(redist, 0x10300) "Interrupt Set-Active Register 0" type(uint32);
80
81    register GICR_ICACTIVER0 addr(redist, 0x10380) "Interrupt Clear-Active Register 0" type(uint32);
82
83    regarray GICR_IPRIORITYR0 addr(redist, 0x10400)[8] "Interrupt Priority Registers" type(uint32);
84
85    register GICR_ICFGR0 addr(redist, 0x10c00) "SGI Configuration Register" type(uint32);
86    register GICR_ICFGR1 addr(redist, 0x10c04) "PPI Configuration Register" type(uint32);
87
88    register GICR_IGRPMODR0 addr(redist, 0x10d00) "Interrupt Group Modifier Register 0" type(uint32);
89
90    register GICR_NSACR0 addr(redist, 0x10e00) "Non-secure Access Control Register" type(uint32);
91};
92