1/* 2 * Copyright (c) 2018, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * gic_v3.dev 11 * 12 * DESCRIPTION: GIC v3 architecture definitions 13 * 14 * See: 15 * GIC v3 Architecture Specification 16 */ 17 18device gic_v3_dist msbfirst (addr dist) "GIC v3 Distributor" { 19 20 register GICD_CTLR_secure addr(dist, 0x0) "Distributor Control Register" { 21 RWP 1 ro "Register Write Pending"; 22 _ 23; 23 E1NWF 1 "Enable 1 of N Wakeup Functionality"; 24 DS 1 "Disable Security"; 25 ARE_NS 1 "Affinity Routing Enable, Non-secure state"; 26 ARE_S 1 "Affinity Routing Enable, Secure state"; 27 _ 1 mbz; 28 EnableGrp1S 1 "Enable Secure Group 1 interrupts"; 29 EnableGrp1NS 1 "Enable Non-secure Group 1 interrupts"; 30 EnableGrp0 1 "Enable Group 0 interrupts"; 31 }; 32 33 34 register GICD_CTLR also addr(dist, 0x0) "Distributor Control Register" { 35 RWP 1 ro "Register Write Pending"; 36 _ 26; 37 ARE_NS 1 "Affinity Routing Enable, Non-secure state"; 38 _ 2 mbz; 39 EnableGrp1A 1 "ARE_NS=1 -> Enable Secure Group 1 interrupts"; 40 EnableGrp1 1 "ARE_NS=1 -> Enable Non-secure Group 1 interrupts"; 41 }; 42 43 register GICD_TYPER rw addr(dist, 0x4) "Interrupt Controller Type Register" { 44 _ 6 mbz; 45 No1N 1 "1 of N SPI interrupts not supported"; 46 A3V 1 "Affinity 3 valid"; 47 IDbits 5 "The number of interrupt identifier bits supported, minus one"; 48 DVIS 1 "Implementation supports Direct Virtual LPI injection"; 49 LPIS 1 "Implementation supports LPIs"; 50 MBIS 1 "Implementation supports message-based interrupts"; 51 LSPI 5 "maximum number of implemented lockable SPI"; 52 SecurityExtn 1 "Indicates whether the GIC implementation supports two Security states"; 53 _ 2 mbz; 54 CPUNumber 3 "Number of PEs that can be used with affinity routing not enabled, minus one"; 55 ITLinesNumber 5 "Maximum SPI INTID supported"; 56 }; 57 58 register GICD_IIDR ro addr(dist, 0x8) "Distributor Implementer Identification Register" { 59 ProductID 8 "Product identifier"; 60 _ 4 mbz; 61 Variant 4 "Variant number"; 62 Revision 4 "Revision number"; 63 Implementer 12 "JEP106 code of implementing company"; 64 }; 65 66 register GICD_STATUSR rw addr(dist, 0x10) "Error Reporting Status Register" { 67 _ 28 mbz; 68 WROD 1 "Write to RO location has been detected"; 69 RWOD 1 "Read of WO location has been detected"; 70 WRD 1 "Write to reserved location has been detected"; 71 RRD 1 "Read to reserved location has been detected"; 72 }; 73 74 register GICD_SETSPI_NSR wo addr(dist, 0x40) "Set Non-secure SPI Pending Register" { 75 _ 22 mbz; 76 INTID 10 "The INTID of the SPI"; 77 }; 78 79 register GICD_CLRSPI_NSR wo addr(dist, 0x48) "Clear Non-secure SPI Pending Register" { 80 _ 22 mbz; 81 INTID 10 "The INTID of the SPI"; 82 }; 83 84 register GICD_SETSPI_SR wo addr(dist, 0x50) "Set Secure SPI Pending Register" { 85 _ 22 mbz; 86 INTID 10 "The INTID of the SPI"; 87 }; 88 89 register GICD_CLRSPI_SR wo addr(dist, 0x58) "Clear Secure SPI Pending Register" { 90 _ 22 mbz; 91 INTID 10 "The INTID of the SPI"; 92 }; 93 94 regarray GICD_IGROUPR addr(dist, 0x80)[32] "Interrupt Group Registers" type(uint32); 95 96 regarray GICD_ISENABLER addr(dist, 0x100)[32] "Interrupt Set-Enable Registers" type(uint32); 97 98 regarray GICD_ICENABLER addr(dist, 0x180)[32] "Interrupt Clear-Enable Registers" type(uint32); 99 100 regarray GICD_ISPENDR addr(dist, 0x200)[32] "Interrupt Set-Pending Registers" type(uint32); 101 102 regarray GICD_ICPENDR addr(dist, 0x280)[32] "Interrupt Clear-Pending Registers" type(uint32); 103 104 regarray GICD_ISACTIVER addr(dist, 0x300)[32] "Interrupt Set-Active Registers" type(uint32); 105 106 regarray GICD_ICACTIVER addr(dist, 0x380)[32] "Interrupt Clear-Active Registers" type(uint32); 107 108 regarray GICD_IPRIORITYR addr(dist, 0x400)[1020] "Interrupt Priority Registers" type(uint8); 109 110 regarray GICD_ITARGETSR addr(dist, 0x800)[255] "Interrupt Processor Targets Registers" type(uint32); 111 112 regarray GICD_ICFGR addr(dist, 0xC00)[64] "Interrupt Configuration Registers" type(uint32); 113 114 regarray GICD_IGRPMODR addr(dist, 0xD00)[32] "Interrupt Group Modifier Registers" type(uint32); 115 116 regarray GICD_NSACR addr(dist, 0xe00)[64] "Non-secure Access Control Registers" type(uint32); 117 118 119 constants TargetFilterList width(2) "SGI forwarding" { 120 CPUTargetList = 0b00 "Forward the interrupt to the CPU interfaces specified by GICD_SGIR.CPUTargetList."; 121 PEAllTarget = 0b01 "Forward the interrupt to all CPU interfaces except that of the PE that requested the interrupt."; 122 PEOnlyTarget = 0b10 "Forward the interrupt only to the CPU interface of the PE that requested the interrupt."; 123 }; 124 125 register GICD_SGIR wo addr(dist, 0xF00) "Software Generated Interrupt Register" { 126 _ 6 mbz; 127 TargetFilterList 2 type(TargetFilterList); 128 CPUTargetList 8 "Forward to CPU interface bit N (only if TargetFilterList==CPUTargetList)"; 129 NSATT 1 "Required group of the SGI"; 130 _ 11 mbz; 131 INTID 4 "INTID of the SGI to forward to the specified CPU interfaces"; 132 }; 133 134 regarray GICD_CPENDSGIR addr(dist, 0xF10)[4] "SGI Clear-Pending Registers" type(uint32); 135 136 regarray GICD_SPENDSGIR addr(dist, 0xF20)[4] "SGI Set-Pending Registers" type(uint32); 137 138 register ICPIDR2 ro addr(dist, 0x0fe8) "Peripheral ID2 Register" { 139 _ 24; 140 ArchRev 4 "GIC architecture revision"; 141 _ 4; 142 }; 143 144 regarray GICD_IROUTER addr(dist, 0x6100)[1020] "Interrupt Routing Registers" { 145 _ 24 mbz; 146 Aff3 8 "Affinity level 3, least significant level field"; 147 Interrupt_Rouing_Mode 1 "Interrupt Routing Mode"; 148 _ 7 mbz; 149 Aff2 8 "Affinity level 2"; 150 Aff1 8 "Affinity level 1"; 151 Aff0 8 "Affinity level 0, most significant level field"; 152 }; 153 154 register GICD_PIDR2 ro addr(dist, 0xffe8) "Peripheral ID2 Register" { 155 _ 24; 156 ArchRev 4 "GIC architecture revision"; 157 _ 4; 158 }; 159}; 160