138451Smsmith/* 238451Smsmith * Copyright (c) 2019, ETH Zurich. All rights reserved. 338451Smsmith * 438451Smsmith * This file is distributed under the terms in the attached LICENSE file. 538451Smsmith * If you do not find this file, copies can be found by writing to: 638451Smsmith * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 738451Smsmith */ 838451Smsmith 938451Smsmith/* 1038451Smsmith * enet.dev 1138451Smsmith * 1238451Smsmith * DESCRIPTION: imx8x network device 1338451Smsmith * 1438451Smsmith * Number refer to i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual 1538451Smsmith */ 1638451Smsmith 1738451Smsmithdevice enet lsbfirst ( addr base ) "Imx8x enet controller" { 1838451Smsmith 1938451Smsmith /**************************************************************************** 2038451Smsmith * 14.6.5.1/3630 Interrupt Event Register 2138451Smsmith ***************************************************************************/ 2238451Smsmith 2338451Smsmith register eir rw addr(base, 0x0004) "Interrupt Event Register" { 2438451Smsmith rxb1 1 rw1c "Receive buffer interrupt class 1"; 2538451Smsmith rxf1 1 rw1c "Receive frame interrupt class 1"; 2650476Speter txb1 1 rw1c "Transmit buffer interrupt class 1"; 2738451Smsmith txf1 1 rw1c "Transmit frame interrupt class 1"; 2838451Smsmith rxb2 1 rw1c "Receive buffer interrupt class 2"; 2938451Smsmith rxf2 1 rw1c "Receive frame interrupt class 2"; 3038451Smsmith txb2 1 rw1c "Transmit buffer interrupt class 2"; 3138451Smsmith txf2 1 rw1c "Transmit frame interrupt class 2"; 3238451Smsmith _ 1 rsvd; 3338451Smsmith parsrf 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRF]."; 3438451Smsmith parsrr 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRR]."; 3538451Smsmith _ 1 rsvd; 3638451Smsmith rxflush0 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_0]"; 3738451Smsmith rxflush1 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_1]"; 3838451Smsmith rxflush2 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_2]"; 3938451Smsmith ts_timer 1 rw1c "TS_TIMER interrupt mask"; 4038451Smsmith ts_avail 1 rw1c "TS_AVAIL interrupt mask"; 4138451Smsmith wakeup 1 rw1c "WAKEUP interrupt mask"; 4238451Smsmith plr 1 rw1c "PLR interrupt mask"; 4338451Smsmith un 1 rw1c "UN interrupt mask"; 4438451Smsmith rl 1 rw1c "RL interrupt mask"; 4538451Smsmith lc 1 rw1c "LC interrupt mask"; 4638451Smsmith eberr 1 rw1c "EBERR interrupt mask"; 4738451Smsmith mii 1 rw1c "MII interrupt mask"; 4838451Smsmith rxb 1 rw1c "RXB interrupt mask"; 4938451Smsmith rxf 1 rw1c "RXF interrupt mask"; 5038451Smsmith txb 1 rw1c "TXB interrupt mask"; 5138451Smsmith txf 1 rw1c "TXF interrupt mask"; 5238451Smsmith gra 1 rw1c "GRA interrupt mask"; 5338451Smsmith babt 1 rw1c "BABT interrupt mask"; 5438451Smsmith babr 1 rw1c "BABR interrupt mask"; 5538451Smsmith _ 1 rsvd; 5638451Smsmith }; 5738451Smsmith 5838451Smsmith 5938451Smsmith /**************************************************************************** 6038451Smsmith * 14.6.5.2/3634 Interrupt Mask Register 61146327Sobrien ***************************************************************************/ 62146327Sobrien 63146327Sobrien register eimr rw addr(base, 0x0008) "Interrupt Mask Register" { 6438451Smsmith rxb1 1 "Receive buffer interrupt class 1"; 6538451Smsmith rxf1 1 "Receive frame interrupt class 1"; 6638451Smsmith txb1 1 "Transmit buffer interrupt class 1"; 6759766Sjlemon txf1 1 "Transmit frame interrupt class 1"; 6864185Sjhb rxb2 1 "Receive buffer interrupt class 2"; 6938451Smsmith rxf2 1 "Receive frame interrupt class 2"; 70135576Sstefanf txb2 1 "Transmit buffer interrupt class 2"; 71135576Sstefanf txf2 1 "Transmit frame interrupt class 2"; 7239665Smsmith _ 1 rsvd; 7338451Smsmith parsrf 1 "Interrupt mask bit corresponding to EIR[PARSRF]."; 7438451Smsmith parsrr 1 "Interrupt mask bit corresponding to EIR[PARSRR]."; 7538451Smsmith _ 1 rsvd; 7638451Smsmith rxflush0 1 "Corresponds to interrupt source EIR[RXFLUSH_0]"; 7738451Smsmith rxflush1 1 "Corresponds to interrupt source EIR[RXFLUSH_1]"; 7855206Speter rxflush2 1 "Corresponds to interrupt source EIR[RXFLUSH_2]"; 7938451Smsmith ts_timer 1 "TS_TIMER interrupt mask"; 8055206Speter ts_avail 1 "TS_AVAIL interrupt mask"; 8138451Smsmith wakeup 1 "WAKEUP interrupt mask"; 8238451Smsmith plr 1 "PLR interrupt mask"; 8338451Smsmith un 1 "UN interrupt mask"; 8438451Smsmith rl 1 "RL interrupt mask"; 8538451Smsmith lc 1 "LC interrupt mask"; 8638451Smsmith eberr 1 "EBERR interrupt mask"; 8738451Smsmith mii 1 "MII interrupt mask"; 8838451Smsmith rxb 1 "RXB interrupt mask"; 8938451Smsmith rxf 1 "RXF interrupt mask"; 9038451Smsmith txb 1 "TXB interrupt mask"; 9138451Smsmith txf 1 "TXF interrupt mask"; 9238451Smsmith gra 1 "GRA interrupt mask"; 9338451Smsmith babt 1 "BABT interrupt mask"; 9438451Smsmith babr 1 "BABR interrupt mask"; 9538451Smsmith _ 1 rsvd; 9638451Smsmith }; 9738451Smsmith 9838451Smsmith 9938451Smsmith /**************************************************************************** 10038451Smsmith * 14.6.5.3/3638 10138451Smsmith ***************************************************************************/ 10238451Smsmith 10338451Smsmith register rdar rw addr(base, 0x0010) "Receive Descriptor Active Register ring0" { 10439468Smsmith _ 24 rsvd; 10539468Smsmith rdar 1 "Receive Descriptor Active"; 10638451Smsmith _ 7 rsvd; 10738451Smsmith }; 10838451Smsmith 10938451Smsmith /**************************************************************************** 11038451Smsmith * 14.6.5.3/3638 11138451Smsmith ***************************************************************************/ 11238451Smsmith 11359766Sjlemon register tdar rw addr(base, 0x0014) "Transmit Descriptor Active Register ring0" { 11438451Smsmith _ 24 rsvd; 11538451Smsmith tdar 1 "Transmit Descriptor Active"; 11638451Smsmith _ 7 rsvd; 11738451Smsmith }; 11838451Smsmith 11938451Smsmith /**************************************************************************** 12038451Smsmith * 14.6.5.5/3640 Ethernet control register 12138451Smsmith ***************************************************************************/ 12238451Smsmith 123108100Sjake register ecr rw addr(base, 0x0024) "Control register" { 12483610Ssobomax reset 1 "Ethernet MAC Reset"; 12538451Smsmith etheren 1 "Ethernet enable"; 12659766Sjlemon magicen 1 "Magic packet detection enable"; 12792494Ssobomax sleep 1 "Sleep Mode enable"; 12838451Smsmith en1588 1 "EN1588 Enable"; 12938451Smsmith speed 1 "Select between 10/100 Mbit (0) and 1000 Mbit (1)"; 13038451Smsmith dbgen 1 "Debug enable"; 13138451Smsmith _ 1 rsvd; 13238451Smsmith dbswp 1 "Descriptor Byte Swapping Enable"; 13338451Smsmith svlanen 1 "S-VLAN enable"; 13438451Smsmith vlanuse2nd 1 "VLAN use second tag"; 13538451Smsmith svlandbl 1 "S-VLAN double tag"; 13638451Smsmith _ 4 rsvd; 13738451Smsmith txc_dly 1 "Transmit clock delay"; 13839468Smsmith rxc_dly 1 "Receive clock delay"; 13938451Smsmith _ 14 rsvd; 14038451Smsmith }; 14164185Sjhb 14264185Sjhb /**************************************************************************** 14338451Smsmith * 14.6.5.6/3643 MII Management Frame Register 14438451Smsmith ***************************************************************************/ 14538451Smsmith 14640774Smsmith register mmfr rw addr(base, 0x0040) "MII Management Frame Register" { 14764185Sjhb data 16 "Data written to or read from PHY register"; 14838451Smsmith ta 2 "Turn Around: needs to be programmed to 10 to be valid"; 14938451Smsmith ra 5 "Register Address"; 15059766Sjlemon pa 5 "Phy address"; 15159766Sjlemon op 2 "Operation Code"; 15259766Sjlemon st 2 "Start of Frame Delimeter"; 15359766Sjlemon }; 15459766Sjlemon 15538451Smsmith /**************************************************************************** 15638451Smsmith * 14.6.5.6/3643 MII Speed Control Register 15738451Smsmith ***************************************************************************/ 15838451Smsmith 15938451Smsmith register mscr rw addr(base, 0x0044) "MII Speed Control Register" { 16038451Smsmith _ 1 rsvd; 16138451Smsmith mii_speed 6 "MII Speed"; 16238451Smsmith dis_pre 1 "Disable preamble"; 16365470Smsmith hold_time 3 "Hold time on MDIO Output"; 16465470Smsmith _ 21 rsvd; 16565470Smsmith }; 16665470Smsmith 16765470Smsmith /**************************************************************************** 16838451Smsmith * 14.6.5.9/3646 Receive Control Register 16938451Smsmith ***************************************************************************/ 170192679Sdfr 17138451Smsmith register rcr rw addr(base, 0x0084) "Receive Control Register" { 17238451Smsmith loop 1 "Internal Loopback"; 17338451Smsmith drt 1 "Disable Receive on Transmit"; 17438451Smsmith mii_mode 1 "Media Independant Interface Mode"; 17538451Smsmith prom 1 "Promiscuous Mode"; 17638451Smsmith bc_rej 1 "Broadcast Frame Reject"; 17738451Smsmith fce 1 "Flow Control Enable"; 17838451Smsmith rgmii_en 1 "RGMII Mode Enable"; 17955181Speter _ 1 rsvd; 18038451Smsmith rmii_mode 1 "RMII Mode Enable"; 18176579Sdcs rmii_10t 1 "Enable 10-Mbits/mode of the RMII or RGMII"; 18276579Sdcs _ 2 rsvd; 18376579Sdcs paden 1 "Enable Frame Padding Remove On Receive"; 18476579Sdcs paufwd 1 "Terminate/Forward Pause Frames"; 18576579Sdcs crcfwd 1 "Terminate/Forward Receive CRC"; 18676579Sdcs cfen 1 "MAC Control Frame Enable"; 18776579Sdcs max_fl 14 "Maximum Frame Length"; 18876579Sdcs nlc 1 "Payload Length Check Disable"; 18976579Sdcs grs 1 "Graceful Receive Stop"; 19076579Sdcs }; 19176579Sdcs 19276579Sdcs /**************************************************************************** 19376579Sdcs * 14.6.5.11/3649 Transmit Control Register 19476579Sdcs ***************************************************************************/ 19576579Sdcs 19676579Sdcs // 14.6.5.10 19776579Sdcs register tcr rw addr(base, 0x000C4) "Transmit Control Register" { 19876579Sdcs gts 1 "Graceful Transmit Stop"; 19976579Sdcs _ 1 rsvd; 20076579Sdcs fden 1 "Full-Duplex Enable"; 20176579Sdcs tfc_pause 1 "Transmit Frame Control Pause"; 20276579Sdcs rfc_pause 1 "Receive Frame Control Pause"; 20376579Sdcs addsel 3 "Source MAC Address Select on Transmit"; 20476579Sdcs addins 1 "Set MAC Address on Transmit"; 20576579Sdcs crcfwd 1 "Forward Frame From Application With CRC"; 20676579Sdcs _ 1 rsvd; 20776579Sdcs _ 21 rsvd; 20876579Sdcs }; 20976579Sdcs 21076579Sdcs /**************************************************************************** 21176579Sdcs * 14.6.5.11/3651 Physical Address Lower Register 21276579Sdcs ***************************************************************************/ 21376579Sdcs 21476579Sdcs // 14.6.5.11 21576579Sdcs register palr rw addr(base, 0x000E4) "Physical Address Lower Register" { 21651169Sdfr paddr1 32 "Pause Address"; 21751169Sdfr }; 21851169Sdfr 21951169Sdfr /**************************************************************************** 22051169Sdfr * 14.6.5.12/3651 Physical Address Upper Register 22151169Sdfr ***************************************************************************/ 22251169Sdfr 22351169Sdfr register paur rw addr(base, 0x000E8) "Physical Address Upper Register" { 22451169Sdfr typ 16 "Always contains 0x8808"; 22551169Sdfr paddr2 16 "Pause Address"; 22639665Smsmith }; 22739665Smsmith 22839665Smsmith /**************************************************************************** 22938451Smsmith * 14.6.5.12/3651 Opcode/Pause Duration Register 23039665Smsmith ***************************************************************************/ 23139665Smsmith 23239665Smsmith register opd rw addr(base, 0x000EC) "Opcode/Pause Duration Register" { 23339665Smsmith pause_dur 16 "Pause duration"; 23439665Smsmith opcode 16 "Opcode Field in Pause Frames"; 23539665Smsmith }; 23639665Smsmith 23739665Smsmith /**************************************************************************** 23839665Smsmith * 14.6.5.16/3654 Descriptor Individual Upper Address 239100392Speter ***************************************************************************/ 240102227Smike 241100392Speter register iaur rw addr(base, 0x00118) "Descriptor Individual Upper Address Reg" { 242102227Smike iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion"; 24338451Smsmith }; 24438451Smsmith 24538451Smsmith /**************************************************************************** 24638451Smsmith * 14.6.5.17/3655 Descriptor Individual Lower Address 24738451Smsmith ***************************************************************************/ 24838451Smsmith 24938451Smsmith register ialr rw addr(base, 0x0011C) "Descriptor Individual Lower Address Reg" { 25038451Smsmith iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion"; 25138451Smsmith }; 25287632Sjhb 25338451Smsmith /**************************************************************************** 25438451Smsmith * 14.6.5.18/3656 Descriptor Group Upper Address 25538451Smsmith ***************************************************************************/ 25638451Smsmith 25738451Smsmith register gaur rw addr(base, 0x00120) "Descriptor Individual Upper Address Reg" { 25859766Sjlemon iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion"; 25938451Smsmith }; 26038451Smsmith 26138451Smsmith /**************************************************************************** 26238451Smsmith * 14.6.5.19/3656 Descriptor Group Lower Address 26338451Smsmith ***************************************************************************/ 26438451Smsmith 26538451Smsmith register galr rw addr(base, 0x00124) "Descriptor Individual Lower Address Reg" { 26642511Smsmith iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion"; 26738451Smsmith }; 26838451Smsmith 26938451Smsmith 27038451Smsmith /**************************************************************************** 27138451Smsmith * 14.6.5.20/3657 Transmit FIFO Watermark Register 27238451Smsmith ***************************************************************************/ 27339468Smsmith register tfwr rw addr(base, 0x00144) "Transmit FIFO Watermark Register " { 27438451Smsmith tfwr 6 "Transmit FIFO Write"; 27540891Smsmith _ 2 rsvd; 27640891Smsmith strfwd 1 "Store and Forward Enable"; 27740891Smsmith _ 23 rsvd; 27840891Smsmith }; 27938451Smsmith 28038451Smsmith /**************************************************************************** 28138451Smsmith * 14.6.5.27/3662 Receive Descriptor Ring 0 Start Register 28238451Smsmith ***************************************************************************/ 28338451Smsmith register rdsr rw addr(base, 0x00180) "Receive Descriptor Ring 0 Start Register" { 28438451Smsmith _ 3 rsvd; 28538451Smsmith start 29 "Pointer to the beginning of receive descriptor queue"; 286121532Speter }; 287121532Speter 28838451Smsmith /**************************************************************************** 28938451Smsmith * 14.6.5.28/3663 Transmit Descriptor Ring 0 Start Register 29038451Smsmith ***************************************************************************/ 29138451Smsmith register tdsr rw addr(base, 0x00184) "Transmit Descriptor Ring 0 Start Register" { 29238451Smsmith _ 3 rsvd; 29338451Smsmith start 29 "Pointer to the beginning of transmit descriptor queue"; 29438451Smsmith }; 29538451Smsmith 29638451Smsmith 29738451Smsmith /**************************************************************************** 29838451Smsmith * 14.6.5.29/3663 Maximum Receive Buffer Size Register ring 0 29938451Smsmith ***************************************************************************/ 30038451Smsmith register mrbr rw addr(base, 0x00188) "Receive Descriptor Ring 0 Start Register" { 30138451Smsmith _ 4 rsvd; 30264185Sjhb start 10 "Receive buffer size in bytes"; 30364185Sjhb _ 18 rsvd; 30464185Sjhb }; 30538451Smsmith 30664185Sjhb /**************************************************************************** 30764185Sjhb * 14.6.5.30/3664 Receive FIFO Section Full Threshold 30838451Smsmith ***************************************************************************/ 30938451Smsmith register rsfl rw addr(base, 0x00190) "Receive FIFO Section Full Threshold" { 31038451Smsmith rx_section_full 10 "Value of Receive FIFO Sectoin Full Threshold"; 31138451Smsmith _ 22 rsvd; 31238451Smsmith }; 31338451Smsmith 31438451Smsmith 31538451Smsmith /**************************************************************************** 31638451Smsmith * 14.6.5.31/3665 Receive FIFO Section Empty Threshold 31738451Smsmith ***************************************************************************/ 31838451Smsmith register rsem rw addr(base, 0x00194) "Receive FIFO Section Empty Threshold" { 31938451Smsmith rx_section_empty 10 "Value of Receive FIFO Sectoin Empty Threshold"; 32038451Smsmith _ 6 rsvd; 32138451Smsmith stat_section_empty 5 "RX Status Section Empty Threshold"; 32238451Smsmith _ 11 rsvd; 32338451Smsmith }; 32438451Smsmith 32538451Smsmith /**************************************************************************** 32638451Smsmith * 14.6.5.32/3665 Receive FIFO Almost Empty Threshold 32738451Smsmith ***************************************************************************/ 32838451Smsmith register raem rw addr(base, 0x00198) "Receive FIFO Almost Empty Threshold" { 32938451Smsmith rx_almost_full 10 "Value of Receive FIFO Almost Empty Threshold"; 33038451Smsmith _ 22 rsvd; 33138451Smsmith }; 33238451Smsmith 33338451Smsmith /**************************************************************************** 33438451Smsmith * 14.6.5.33/3666 Receive FIFO Almost Empty Threshold 33538451Smsmith ***************************************************************************/ 33638451Smsmith register rafl rw addr(base, 0x0019C) "Receive FIFO Almost Full Threshold" { 33738451Smsmith rx_almost_empty 10 "Value of Receive FIFO Almost Full Threshold"; 33897776Ssobomax _ 22 rsvd; 33938451Smsmith }; 34038451Smsmith 34138451Smsmith 34238451Smsmith /**************************************************************************** 34338451Smsmith * 14.6.5.49/3679 Tx Packet Count Statistic Register 34438451Smsmith ***************************************************************************/ 34538451Smsmith register rmon_t_packets rw addr(base, 0x00204) "Tx Packet Count Statistic Register" { 34639468Smsmith count 16 "Number of packets sent"; 34738451Smsmith _ 16 rsvd; 34855137Speter }; 34955137Speter 35038451Smsmith /**************************************************************************** 35138451Smsmith * 14.6.5.50/3680 Tx Broadcast Packet Count Statistic Register 35259766Sjlemon ***************************************************************************/ 35338451Smsmith register rmon_t_bc_pkt rw addr(base, 0x00208) "Tx Broadcast Packet Count Statistic Register" { 35459766Sjlemon count 16 "Number of packets sent"; 35538451Smsmith _ 16 rsvd; 35638451Smsmith }; 35738451Smsmith 35838451Smsmith /**************************************************************************** 35938451Smsmith * 14.6.5.51/3680 Tx Multicast Packet Count Statistic Register 36038451Smsmith ***************************************************************************/ 36138451Smsmith register rmon_t_mc_pkt rw addr(base, 0x0020C) "Tx Multicast Packet Count Statistic Register" { 36239672Sdfr count 16 "Number of packets sent"; 36338451Smsmith _ 16 rsvd; 364124570Sjhb }; 36538451Smsmith 36638451Smsmith /**************************************************************************** 36738451Smsmith * 14.6.5.52/3681 Tx Packets with CRC/Align Error Statistic Register 36890868Smike ***************************************************************************/ 36990868Smike register rmon_t_crc_align rw addr(base, 0x00210) "Tx Packets with CRC/Align Error Statistic Register" { 37090868Smike count 16 "Number of packets sent"; 37191959Smike _ 16 rsvd; 37291959Smike }; 37391959Smike 37491959Smike /**************************************************************************** 37591959Smike * 14.6.5.53/3681 Tx Packets Less Than Bytes and Good CRC Statistics 37691959Smike ***************************************************************************/ 37791959Smike register rmon_t_undersize rw addr(base, 0x00214) "Tx Packets Less Than Bytes and Good CRC Statistics" { 37891959Smike count 16 "Number of packets sent"; 37991959Smike _ 16 rsvd; 38091959Smike }; 38190868Smike 38290868Smike /**************************************************************************** 38390868Smike * 14.6.5.54/3681 Tx Packets GT MAX_FL bytes and Good CRC Statistics 38490868Smike ***************************************************************************/ 38591959Smike register rmon_t_oversize rw addr(base, 0x00218) "Tx Packets GT MAX_FL bytes and Good CRC Statistics" { 38690868Smike count 16 "Number of packets sent"; 387100394Speter _ 16 rsvd; 388100394Speter }; 389100394Speter 390100394Speter 39139672Sdfr /**************************************************************************** 392100394Speter * 14.6.5.55/3681 Tx Packets Less Than Bytes and bad CRC Statistics 393100394Speter ***************************************************************************/ 394100394Speter register rmon_t_frag rw addr(base, 0x0021C) "Tx Packets Less Than Bytes and bad CRC Statistics" { 395100394Speter count 16 "Number of packets sent"; 396100394Speter _ 16 rsvd; 397100394Speter }; 398102216Sscottl 399100394Speter /**************************************************************************** 400100394Speter * 14.6.5.54/3682 Tx Packets GT MAX_FL bytes and bad CRC Statistics 401100394Speter ***************************************************************************/ 40239672Sdfr register rmon_t_jab rw addr(base, 0x00220) "Tx Packets GT MAX_FL bytes and bad CRC Statistics" { 403146327Sobrien count 16 "Number of packets sent"; 404146327Sobrien _ 16 rsvd; 405 }; 406 407 /**************************************************************************** 408 * 14.6.5.55/3683 Tx Collision Count Statistic Register 409 ***************************************************************************/ 410 register rmon_t_col rw addr(base, 0x00224) "Tx Collision Count Statistic Register" { 411 count 16 "Number of packets sent"; 412 _ 16 rsvd; 413 }; 414 415 /**************************************************************************** 416 * 14.6.5.79/3766 Rx Packet Count Statistic Register 417 ***************************************************************************/ 418 register rmon_r_packets rw addr(base, 0x00284) "Rx Packet Count Statistic Register" { 419 count 16 "Number of packets received"; 420 _ 16 rsvd; 421 }; 422 423 424 /**************************************************************************** 425 * 14.6.5.81/3767 Rx Packets with CRC/Align Error Statistic Register 426 ***************************************************************************/ 427 register rmon_r_packets_crc_align rw addr(base, 0x00290) "Rx Packets with CRC/Align Error Statistic Register" { 428 count 16 "Number of packets received with CRC or align error"; 429 _ 16 rsvd; 430 }; 431 432 433 /**************************************************************************** 434 * 14.6.5.94/3767 Rx Octets Statistic Register 435 ***************************************************************************/ 436 register rmon_r_octets rw addr(base, 0x002C4) "Rx Packets with CRC/Align Error Statistic Register" { 437 count 32 "Number of received octets"; 438 }; 439 440 441 /**************************************************************************** 442 * 14.6.5.95/3773 Frame not Counted Correctly Statistic Register 443 ***************************************************************************/ 444 register iee_r_drop rw addr(base, 0x002C8) "Frame not Counted Correctly Statistic Register" { 445 count 16 "Frame count"; 446 _ 16 rsvd; 447 }; 448 datatype bufdesc "Legacy descriptor" { 449 len 16 "Data length"; 450 sc 16 "Control and status info"; 451 addr 32 "Buffer address"; 452 }; 453 454 /* 455 datatype bufdesc_ex "Enhanced descriptor" { 456 sc 16 "Control and status info"; 457 len 16 "Data length"; 458 addr 32 "Buffer address"; 459 esc 32 ""; 460 prot 32 ""; 461 ts 32 ""; 462 res0 64 ""; 463 }; 464 */ 465 466}; 467