1/* 2 * Copyright (c) 2019, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * enet.dev 11 * 12 * DESCRIPTION: imx8x network device 13 * 14 * Number refer to i.MX 8DualXPlus/8QuadXPlus Applications Processor Reference Manual 15 */ 16 17device enet lsbfirst ( addr base ) "Imx8x enet controller" { 18 19 /**************************************************************************** 20 * 14.6.5.1/3630 Interrupt Event Register 21 ***************************************************************************/ 22 23 register eir rw addr(base, 0x0004) "Interrupt Event Register" { 24 rxb1 1 rw1c "Receive buffer interrupt class 1"; 25 rxf1 1 rw1c "Receive frame interrupt class 1"; 26 txb1 1 rw1c "Transmit buffer interrupt class 1"; 27 txf1 1 rw1c "Transmit frame interrupt class 1"; 28 rxb2 1 rw1c "Receive buffer interrupt class 2"; 29 rxf2 1 rw1c "Receive frame interrupt class 2"; 30 txb2 1 rw1c "Transmit buffer interrupt class 2"; 31 txf2 1 rw1c "Transmit frame interrupt class 2"; 32 _ 1 rsvd; 33 parsrf 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRF]."; 34 parsrr 1 rw1c "Interrupt mask bit corresponding to EIR[PARSRR]."; 35 _ 1 rsvd; 36 rxflush0 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_0]"; 37 rxflush1 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_1]"; 38 rxflush2 1 rw1c "Corresponds to interrupt source EIR[RXFLUSH_2]"; 39 ts_timer 1 rw1c "TS_TIMER interrupt mask"; 40 ts_avail 1 rw1c "TS_AVAIL interrupt mask"; 41 wakeup 1 rw1c "WAKEUP interrupt mask"; 42 plr 1 rw1c "PLR interrupt mask"; 43 un 1 rw1c "UN interrupt mask"; 44 rl 1 rw1c "RL interrupt mask"; 45 lc 1 rw1c "LC interrupt mask"; 46 eberr 1 rw1c "EBERR interrupt mask"; 47 mii 1 rw1c "MII interrupt mask"; 48 rxb 1 rw1c "RXB interrupt mask"; 49 rxf 1 rw1c "RXF interrupt mask"; 50 txb 1 rw1c "TXB interrupt mask"; 51 txf 1 rw1c "TXF interrupt mask"; 52 gra 1 rw1c "GRA interrupt mask"; 53 babt 1 rw1c "BABT interrupt mask"; 54 babr 1 rw1c "BABR interrupt mask"; 55 _ 1 rsvd; 56 }; 57 58 59 /**************************************************************************** 60 * 14.6.5.2/3634 Interrupt Mask Register 61 ***************************************************************************/ 62 63 register eimr rw addr(base, 0x0008) "Interrupt Mask Register" { 64 rxb1 1 "Receive buffer interrupt class 1"; 65 rxf1 1 "Receive frame interrupt class 1"; 66 txb1 1 "Transmit buffer interrupt class 1"; 67 txf1 1 "Transmit frame interrupt class 1"; 68 rxb2 1 "Receive buffer interrupt class 2"; 69 rxf2 1 "Receive frame interrupt class 2"; 70 txb2 1 "Transmit buffer interrupt class 2"; 71 txf2 1 "Transmit frame interrupt class 2"; 72 _ 1 rsvd; 73 parsrf 1 "Interrupt mask bit corresponding to EIR[PARSRF]."; 74 parsrr 1 "Interrupt mask bit corresponding to EIR[PARSRR]."; 75 _ 1 rsvd; 76 rxflush0 1 "Corresponds to interrupt source EIR[RXFLUSH_0]"; 77 rxflush1 1 "Corresponds to interrupt source EIR[RXFLUSH_1]"; 78 rxflush2 1 "Corresponds to interrupt source EIR[RXFLUSH_2]"; 79 ts_timer 1 "TS_TIMER interrupt mask"; 80 ts_avail 1 "TS_AVAIL interrupt mask"; 81 wakeup 1 "WAKEUP interrupt mask"; 82 plr 1 "PLR interrupt mask"; 83 un 1 "UN interrupt mask"; 84 rl 1 "RL interrupt mask"; 85 lc 1 "LC interrupt mask"; 86 eberr 1 "EBERR interrupt mask"; 87 mii 1 "MII interrupt mask"; 88 rxb 1 "RXB interrupt mask"; 89 rxf 1 "RXF interrupt mask"; 90 txb 1 "TXB interrupt mask"; 91 txf 1 "TXF interrupt mask"; 92 gra 1 "GRA interrupt mask"; 93 babt 1 "BABT interrupt mask"; 94 babr 1 "BABR interrupt mask"; 95 _ 1 rsvd; 96 }; 97 98 99 /**************************************************************************** 100 * 14.6.5.3/3638 101 ***************************************************************************/ 102 103 register rdar rw addr(base, 0x0010) "Receive Descriptor Active Register ring0" { 104 _ 24 rsvd; 105 rdar 1 "Receive Descriptor Active"; 106 _ 7 rsvd; 107 }; 108 109 /**************************************************************************** 110 * 14.6.5.3/3638 111 ***************************************************************************/ 112 113 register tdar rw addr(base, 0x0014) "Transmit Descriptor Active Register ring0" { 114 _ 24 rsvd; 115 tdar 1 "Transmit Descriptor Active"; 116 _ 7 rsvd; 117 }; 118 119 /**************************************************************************** 120 * 14.6.5.5/3640 Ethernet control register 121 ***************************************************************************/ 122 123 register ecr rw addr(base, 0x0024) "Control register" { 124 reset 1 "Ethernet MAC Reset"; 125 etheren 1 "Ethernet enable"; 126 magicen 1 "Magic packet detection enable"; 127 sleep 1 "Sleep Mode enable"; 128 en1588 1 "EN1588 Enable"; 129 speed 1 "Select between 10/100 Mbit (0) and 1000 Mbit (1)"; 130 dbgen 1 "Debug enable"; 131 _ 1 rsvd; 132 dbswp 1 "Descriptor Byte Swapping Enable"; 133 svlanen 1 "S-VLAN enable"; 134 vlanuse2nd 1 "VLAN use second tag"; 135 svlandbl 1 "S-VLAN double tag"; 136 _ 4 rsvd; 137 txc_dly 1 "Transmit clock delay"; 138 rxc_dly 1 "Receive clock delay"; 139 _ 14 rsvd; 140 }; 141 142 /**************************************************************************** 143 * 14.6.5.6/3643 MII Management Frame Register 144 ***************************************************************************/ 145 146 register mmfr rw addr(base, 0x0040) "MII Management Frame Register" { 147 data 16 "Data written to or read from PHY register"; 148 ta 2 "Turn Around: needs to be programmed to 10 to be valid"; 149 ra 5 "Register Address"; 150 pa 5 "Phy address"; 151 op 2 "Operation Code"; 152 st 2 "Start of Frame Delimeter"; 153 }; 154 155 /**************************************************************************** 156 * 14.6.5.6/3643 MII Speed Control Register 157 ***************************************************************************/ 158 159 register mscr rw addr(base, 0x0044) "MII Speed Control Register" { 160 _ 1 rsvd; 161 mii_speed 6 "MII Speed"; 162 dis_pre 1 "Disable preamble"; 163 hold_time 3 "Hold time on MDIO Output"; 164 _ 21 rsvd; 165 }; 166 167 /**************************************************************************** 168 * 14.6.5.9/3646 Receive Control Register 169 ***************************************************************************/ 170 171 register rcr rw addr(base, 0x0084) "Receive Control Register" { 172 loop 1 "Internal Loopback"; 173 drt 1 "Disable Receive on Transmit"; 174 mii_mode 1 "Media Independant Interface Mode"; 175 prom 1 "Promiscuous Mode"; 176 bc_rej 1 "Broadcast Frame Reject"; 177 fce 1 "Flow Control Enable"; 178 rgmii_en 1 "RGMII Mode Enable"; 179 _ 1 rsvd; 180 rmii_mode 1 "RMII Mode Enable"; 181 rmii_10t 1 "Enable 10-Mbits/mode of the RMII or RGMII"; 182 _ 2 rsvd; 183 paden 1 "Enable Frame Padding Remove On Receive"; 184 paufwd 1 "Terminate/Forward Pause Frames"; 185 crcfwd 1 "Terminate/Forward Receive CRC"; 186 cfen 1 "MAC Control Frame Enable"; 187 max_fl 14 "Maximum Frame Length"; 188 nlc 1 "Payload Length Check Disable"; 189 grs 1 "Graceful Receive Stop"; 190 }; 191 192 /**************************************************************************** 193 * 14.6.5.11/3649 Transmit Control Register 194 ***************************************************************************/ 195 196 // 14.6.5.10 197 register tcr rw addr(base, 0x000C4) "Transmit Control Register" { 198 gts 1 "Graceful Transmit Stop"; 199 _ 1 rsvd; 200 fden 1 "Full-Duplex Enable"; 201 tfc_pause 1 "Transmit Frame Control Pause"; 202 rfc_pause 1 "Receive Frame Control Pause"; 203 addsel 3 "Source MAC Address Select on Transmit"; 204 addins 1 "Set MAC Address on Transmit"; 205 crcfwd 1 "Forward Frame From Application With CRC"; 206 _ 1 rsvd; 207 _ 21 rsvd; 208 }; 209 210 /**************************************************************************** 211 * 14.6.5.11/3651 Physical Address Lower Register 212 ***************************************************************************/ 213 214 // 14.6.5.11 215 register palr rw addr(base, 0x000E4) "Physical Address Lower Register" { 216 paddr1 32 "Pause Address"; 217 }; 218 219 /**************************************************************************** 220 * 14.6.5.12/3651 Physical Address Upper Register 221 ***************************************************************************/ 222 223 register paur rw addr(base, 0x000E8) "Physical Address Upper Register" { 224 typ 16 "Always contains 0x8808"; 225 paddr2 16 "Pause Address"; 226 }; 227 228 /**************************************************************************** 229 * 14.6.5.12/3651 Opcode/Pause Duration Register 230 ***************************************************************************/ 231 232 register opd rw addr(base, 0x000EC) "Opcode/Pause Duration Register" { 233 pause_dur 16 "Pause duration"; 234 opcode 16 "Opcode Field in Pause Frames"; 235 }; 236 237 /**************************************************************************** 238 * 14.6.5.16/3654 Descriptor Individual Upper Address 239 ***************************************************************************/ 240 241 register iaur rw addr(base, 0x00118) "Descriptor Individual Upper Address Reg" { 242 iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion"; 243 }; 244 245 /**************************************************************************** 246 * 14.6.5.17/3655 Descriptor Individual Lower Address 247 ***************************************************************************/ 248 249 register ialr rw addr(base, 0x0011C) "Descriptor Individual Lower Address Reg" { 250 iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion"; 251 }; 252 253 /**************************************************************************** 254 * 14.6.5.18/3656 Descriptor Group Upper Address 255 ***************************************************************************/ 256 257 register gaur rw addr(base, 0x00120) "Descriptor Individual Upper Address Reg" { 258 iaddr1 32 "Upper 32 bits of 64-bit hash table used in address regcogntion"; 259 }; 260 261 /**************************************************************************** 262 * 14.6.5.19/3656 Descriptor Group Lower Address 263 ***************************************************************************/ 264 265 register galr rw addr(base, 0x00124) "Descriptor Individual Lower Address Reg" { 266 iaddr2 32 "Lower 32 bits of 64-bit hash table used in address regcogntion"; 267 }; 268 269 270 /**************************************************************************** 271 * 14.6.5.20/3657 Transmit FIFO Watermark Register 272 ***************************************************************************/ 273 register tfwr rw addr(base, 0x00144) "Transmit FIFO Watermark Register " { 274 tfwr 6 "Transmit FIFO Write"; 275 _ 2 rsvd; 276 strfwd 1 "Store and Forward Enable"; 277 _ 23 rsvd; 278 }; 279 280 /**************************************************************************** 281 * 14.6.5.27/3662 Receive Descriptor Ring 0 Start Register 282 ***************************************************************************/ 283 register rdsr rw addr(base, 0x00180) "Receive Descriptor Ring 0 Start Register" { 284 _ 3 rsvd; 285 start 29 "Pointer to the beginning of receive descriptor queue"; 286 }; 287 288 /**************************************************************************** 289 * 14.6.5.28/3663 Transmit Descriptor Ring 0 Start Register 290 ***************************************************************************/ 291 register tdsr rw addr(base, 0x00184) "Transmit Descriptor Ring 0 Start Register" { 292 _ 3 rsvd; 293 start 29 "Pointer to the beginning of transmit descriptor queue"; 294 }; 295 296 297 /**************************************************************************** 298 * 14.6.5.29/3663 Maximum Receive Buffer Size Register ring 0 299 ***************************************************************************/ 300 register mrbr rw addr(base, 0x00188) "Receive Descriptor Ring 0 Start Register" { 301 _ 4 rsvd; 302 start 10 "Receive buffer size in bytes"; 303 _ 18 rsvd; 304 }; 305 306 /**************************************************************************** 307 * 14.6.5.30/3664 Receive FIFO Section Full Threshold 308 ***************************************************************************/ 309 register rsfl rw addr(base, 0x00190) "Receive FIFO Section Full Threshold" { 310 rx_section_full 10 "Value of Receive FIFO Sectoin Full Threshold"; 311 _ 22 rsvd; 312 }; 313 314 315 /**************************************************************************** 316 * 14.6.5.31/3665 Receive FIFO Section Empty Threshold 317 ***************************************************************************/ 318 register rsem rw addr(base, 0x00194) "Receive FIFO Section Empty Threshold" { 319 rx_section_empty 10 "Value of Receive FIFO Sectoin Empty Threshold"; 320 _ 6 rsvd; 321 stat_section_empty 5 "RX Status Section Empty Threshold"; 322 _ 11 rsvd; 323 }; 324 325 /**************************************************************************** 326 * 14.6.5.32/3665 Receive FIFO Almost Empty Threshold 327 ***************************************************************************/ 328 register raem rw addr(base, 0x00198) "Receive FIFO Almost Empty Threshold" { 329 rx_almost_full 10 "Value of Receive FIFO Almost Empty Threshold"; 330 _ 22 rsvd; 331 }; 332 333 /**************************************************************************** 334 * 14.6.5.33/3666 Receive FIFO Almost Empty Threshold 335 ***************************************************************************/ 336 register rafl rw addr(base, 0x0019C) "Receive FIFO Almost Full Threshold" { 337 rx_almost_empty 10 "Value of Receive FIFO Almost Full Threshold"; 338 _ 22 rsvd; 339 }; 340 341 342 /**************************************************************************** 343 * 14.6.5.49/3679 Tx Packet Count Statistic Register 344 ***************************************************************************/ 345 register rmon_t_packets rw addr(base, 0x00204) "Tx Packet Count Statistic Register" { 346 count 16 "Number of packets sent"; 347 _ 16 rsvd; 348 }; 349 350 /**************************************************************************** 351 * 14.6.5.50/3680 Tx Broadcast Packet Count Statistic Register 352 ***************************************************************************/ 353 register rmon_t_bc_pkt rw addr(base, 0x00208) "Tx Broadcast Packet Count Statistic Register" { 354 count 16 "Number of packets sent"; 355 _ 16 rsvd; 356 }; 357 358 /**************************************************************************** 359 * 14.6.5.51/3680 Tx Multicast Packet Count Statistic Register 360 ***************************************************************************/ 361 register rmon_t_mc_pkt rw addr(base, 0x0020C) "Tx Multicast Packet Count Statistic Register" { 362 count 16 "Number of packets sent"; 363 _ 16 rsvd; 364 }; 365 366 /**************************************************************************** 367 * 14.6.5.52/3681 Tx Packets with CRC/Align Error Statistic Register 368 ***************************************************************************/ 369 register rmon_t_crc_align rw addr(base, 0x00210) "Tx Packets with CRC/Align Error Statistic Register" { 370 count 16 "Number of packets sent"; 371 _ 16 rsvd; 372 }; 373 374 /**************************************************************************** 375 * 14.6.5.53/3681 Tx Packets Less Than Bytes and Good CRC Statistics 376 ***************************************************************************/ 377 register rmon_t_undersize rw addr(base, 0x00214) "Tx Packets Less Than Bytes and Good CRC Statistics" { 378 count 16 "Number of packets sent"; 379 _ 16 rsvd; 380 }; 381 382 /**************************************************************************** 383 * 14.6.5.54/3681 Tx Packets GT MAX_FL bytes and Good CRC Statistics 384 ***************************************************************************/ 385 register rmon_t_oversize rw addr(base, 0x00218) "Tx Packets GT MAX_FL bytes and Good CRC Statistics" { 386 count 16 "Number of packets sent"; 387 _ 16 rsvd; 388 }; 389 390 391 /**************************************************************************** 392 * 14.6.5.55/3681 Tx Packets Less Than Bytes and bad CRC Statistics 393 ***************************************************************************/ 394 register rmon_t_frag rw addr(base, 0x0021C) "Tx Packets Less Than Bytes and bad CRC Statistics" { 395 count 16 "Number of packets sent"; 396 _ 16 rsvd; 397 }; 398 399 /**************************************************************************** 400 * 14.6.5.54/3682 Tx Packets GT MAX_FL bytes and bad CRC Statistics 401 ***************************************************************************/ 402 register rmon_t_jab rw addr(base, 0x00220) "Tx Packets GT MAX_FL bytes and bad CRC Statistics" { 403 count 16 "Number of packets sent"; 404 _ 16 rsvd; 405 }; 406 407 /**************************************************************************** 408 * 14.6.5.55/3683 Tx Collision Count Statistic Register 409 ***************************************************************************/ 410 register rmon_t_col rw addr(base, 0x00224) "Tx Collision Count Statistic Register" { 411 count 16 "Number of packets sent"; 412 _ 16 rsvd; 413 }; 414 415 /**************************************************************************** 416 * 14.6.5.79/3766 Rx Packet Count Statistic Register 417 ***************************************************************************/ 418 register rmon_r_packets rw addr(base, 0x00284) "Rx Packet Count Statistic Register" { 419 count 16 "Number of packets received"; 420 _ 16 rsvd; 421 }; 422 423 424 /**************************************************************************** 425 * 14.6.5.81/3767 Rx Packets with CRC/Align Error Statistic Register 426 ***************************************************************************/ 427 register rmon_r_packets_crc_align rw addr(base, 0x00290) "Rx Packets with CRC/Align Error Statistic Register" { 428 count 16 "Number of packets received with CRC or align error"; 429 _ 16 rsvd; 430 }; 431 432 433 /**************************************************************************** 434 * 14.6.5.94/3767 Rx Octets Statistic Register 435 ***************************************************************************/ 436 register rmon_r_octets rw addr(base, 0x002C4) "Rx Packets with CRC/Align Error Statistic Register" { 437 count 32 "Number of received octets"; 438 }; 439 440 441 /**************************************************************************** 442 * 14.6.5.95/3773 Frame not Counted Correctly Statistic Register 443 ***************************************************************************/ 444 register iee_r_drop rw addr(base, 0x002C8) "Frame not Counted Correctly Statistic Register" { 445 count 16 "Frame count"; 446 _ 16 rsvd; 447 }; 448 datatype bufdesc "Legacy descriptor" { 449 len 16 "Data length"; 450 sc 16 "Control and status info"; 451 addr 32 "Buffer address"; 452 }; 453 454 /* 455 datatype bufdesc_ex "Enhanced descriptor" { 456 sc 16 "Control and status info"; 457 len 16 "Data length"; 458 addr 32 "Buffer address"; 459 esc 32 ""; 460 prot 32 ""; 461 ts 32 ""; 462 res0 64 ""; 463 }; 464 */ 465 466}; 467