1/* 2 * Copyright (c) 2013, University of Washington. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * e10k_vf.dev 11 * 12 * DESCRIPTION: Intel 82599 10 GbE Controller Virtual Function 13 * 14 * Numbers in comments refer to the Intel 82599 10 GbE Controller Datasheet, 15 * Revison 2.76, September 2012 16 */ 17 18device e10k_vf lsbfirst ( addr base ) "Intel 82599 10 GbE Controller Virtual Function" { 19 20 /************************************ 21 * 8.3.5.1 General control registers--VF 22 ***********************************/ 23 24 // 8.3.5.1.1 25 register vfctrl wo addr(base, 0x00000) "VF control" { 26 _ 26 rsvd; 27 rst 1 "Device reset"; 28 _ 5 rsvd; 29 }; 30 31 constants lanid "LAN ID" { 32 lan_0 = 0b00 "LAN 0"; 33 lan_1 = 0b01 "LAN 1"; 34 lan_not_u1 = 0b10 "LAN ID not used"; 35 lan_not_u2 = 0b11 "LAN ID not used"; 36 }; 37 38 // 8.3.5.1.2 39 register vfstatus ro addr(base, 0x00008) "VF status" { 40 _ 2; 41 lan_id 2 type(lanid) "LAN ID"; 42 _ 3; 43 link_up 1 "Linkup Status Indication"; 44 _ 2; 45 num_vfs 8 "Num VFs"; 46 iov_active 1 "IOV Active"; 47 pcie_mes 1 "PCIe Master Enable Status"; 48 _ 12; 49 }; 50 51 // 8.3.5.1.3 52 constants mac_lnkmode "MAC link mode status" { 53 lms_1g = 0b00 "1 GbE"; 54 lms_10g_par = 0b01 "10 GbE parallel"; 55 lms_10g_ser = 0b10 "10 GbE serial"; 56 lms_aneg = 0b11 "auto-negotiation"; 57 }; 58 59 constants link_speed "MAC link speed status" { 60 ls_100m = 0b01 "100 Mb/s"; 61 ls_1g = 0b10 "1 GbE"; 62 ls_10g = 0b11 "10 GbE"; 63 }; 64 65 register vflinks ro addr(base, 0x00010) "VF Link Status Register" { 66 kxsig_det 1 "A signal is present"; 67 fecsig_det 1 "FEC reports signal detected"; 68 fecblk_lck 1 "FEC reached block lock"; 69 krhberr 1 "10GbE serial KR_PCS high error rate"; 70 krpcsbl 1 "10 GbE serial PCS block lock"; 71 kxr_annprcv 1 "KX/KX4/KR AN Next Page Received"; 72 kxr_anprcv 1 "KX/KX4/KR Backplane Auto Negotiation Page Received"; 73 lnk_stat 1 "Link Up and there was no link down from last time read"; 74 kx4sig_det 4 "Signal Detect of 10 GbE Parallel (KX4, CX4 or XAUI) (1bit per lane)"; 75 krsig_det 1 "Signal Detect of 10 GbE serial (KR or SFI)"; 76 l10g_syncst 4 "10G Parallel lane sync status (1bit per lane)"; 77 l10g_algst 1 "10 GbE align_status"; 78 l1g_syncst 1 "1G sync_status"; 79 kxr_anrxid 1 "KX/KX4/KR Backplane Auto Negotiation Rx Idle"; 80 l1g_anen 1 "PCS_1 GbE auto-negotiation is enabled"; 81 l1g_lnken 1 "1 GbE PCS enabled for 1 GbE and SGMII operation"; 82 l10g_lnken 1 "XGXS Enabled for 10 GbE operation"; 83 fec_en 1 "Status of forwarderrorcorrection in 10 GbE serial link"; 84 l10g_seren 1 "Status of 10 GbE serial PCS (KR PCS) for KR or SFI operation"; 85 sgmii_en 1 "Status of SGMII operation"; 86 mlink_mode 2 type (mac_lnkmode) "MAC link mode status"; 87 lnk_speed 2 type (link_speed) "MAC link speed status"; 88 lnk_up 1 "Link is up"; 89 kxr_ancomp 1 "KX/KX4/KR backplane auto-negotiation has completed successfully"; 90 }; 91 92 // NYI: 93 // 8.3.5.1.4 VF Free Running Timer (VFFRTIMER) 94 // 8.3.5.1.5 VF Mailbox (VFMailbox) 95 // 8.3.5.1.6 VF Mailbox Memory (VFMBMEM) 96 97 // 8.3.5.1.7 98 register vfrxmemwrap ro addr(base, 0x03190) "VF Rx Packet Buffer Flush Detect" { 99 tc0_wrap 3 "Packet Buffer 0 Wrap Around Counter"; 100 tc0_empty 1 "Packet Buffer 0 Empty"; 101 tc1_wrap 3 "Packet Buffer 1 Wrap Around Counter"; 102 tc1_empty 1 "Packet Buffer 1 Empty"; 103 tc2_wrap 3 "Packet Buffer 2 Wrap Around Counter"; 104 tc2_empty 1 "Packet Buffer 2 Empty"; 105 tc3_wrap 3 "Packet Buffer 3 Wrap Around Counter"; 106 tc3_empty 1 "Packet Buffer 3 Empty"; 107 tc4_wrap 3 "Packet Buffer 4 Wrap Around Counter"; 108 tc4_empty 1 "Packet Buffer 4 Empty"; 109 tc5_wrap 3 "Packet Buffer 5 Wrap Around Counter"; 110 tc5_empty 1 "Packet Buffer 5 Empty"; 111 tc6_wrap 3 "Packet Buffer 6 Wrap Around Counter"; 112 tc6_empty 1 "Packet Buffer 6 Empty"; 113 tc7_wrap 3 "Packet Buffer 7 Wrap Around Counter"; 114 tc7_empty 1 "Packet Buffer 7 Empty"; 115 }; 116 117 /************************************ 118 * 8.3.5.2 Interrupt Registers--VF 119 ***********************************/ 120 121 // 8.3.5.2.1 122 register vfeicr rw1c addr(base, 0x00100) "VF Extended Interrupt Cause" { 123 msix 3 "Indicates an interrupt cause mapped to MSI-X vectors 2:0"; 124 _ 29 rsvd; 125 }; 126 127 // 8.3.5.2.2 128 register vfeics wo addr(base, 0x00104) "VF Extended Interrupt Cause Set" { 129 msix 3 "Sets to corresponding EICR bit of MSI-X vectors 2:0"; 130 _ 29 rsvd; 131 }; 132 133 // 8.3.5.2.3 134 register vfeims rw addr(base, 0x00108) "VF Extended Interrupt Mask Set/Read" { 135 msix 3 "Set mask bit for the corresponding EICR bit of MSI-X vectors 2:0"; 136 _ 29 rsvd; 137 }; 138 139 // 8.3.5.2.4 140 register vfeimc wo addr(base, 0x0010c) "VF Extended Interrupt Mask Clear" { 141 msix 3 "Clear mask bit for the corresponding EICR bit of MSI-X vectors 2:0"; 142 _ 29 rsvd; 143 }; 144 145 // 8.3.5.2.5 146 register vfeiam rw addr(base, 0x00114) "VF Extended Interrupt Auto Mask Enable" { 147 msix 3 "Auto mask bit for the corresponding EICR bit of MSI-X vectors 2:0"; 148 _ 29 rsvd; 149 }; 150 151 // 8.3.5.2.6 152/* 153 regtype vfeitrn "VF Extended Interrupt Throttle Register Type" { 154 _ 3 rsvd; 155 itr_int 9 "Minimum inter-interrupt interval"; 156 _ 3 rsvd; 157 lli_mod 1 "LLI Moderation"; 158 lli_credit 5 "LLI Credit"; 159 itr_count 7 "ITR Counter"; 160 _ 3 rsvd; 161 cnt_wdis 1 "CNT_WDIS"; 162 }; 163*/ 164 // XXX: Not sure if this is correct... 165 regarray vfeitr rw addr(base, 0x00820) [2] 166 "VF Extended Interrupt Mask Set/Read #0-#1" 167 type(uint32); 168 169 // 8.3.5.2.7 170 regarray vfivar rw addr(base, 0x00120) [4] "VF Interrupt Vector Allocation Registers" { 171 i_alloc0 1 "Defines the MSI-X vector (0 or 1) assigned to Rx queue 2*N for IVAR N register (N = 0..3)"; 172 _ 6 rsvd; 173 i_allocval0 1 "Interrupt allocation 0 valid"; 174 i_alloc1 1 "The interrupt allocation for Tx queue 2n"; 175 _ 6 rsvd; 176 i_allocval1 1 "Interrupt allocation 1 valid"; 177 i_alloc2 1 "The interrupt allocation for Rx queue 2n+1"; 178 _ 6 rsvd; 179 i_allocval2 1 "Interrupt allocation 2 valid"; 180 i_alloc3 1 "The interrupt allocation for Tx queue 2n+1"; 181 _ 6 rsvd; 182 i_allocval3 1 "Interrupt allocation 3 valid"; 183 }; 184 185 // 8.3.5.2.8 186 register vfivar_misc rw addr(base, 0x00140) "VF Miscellaneous Interrupt Vector Allocation" { 187 i_alloc0 2 "MSI-X vector assigned to the mailbox interrupt"; 188 _ 5 rsvd; 189 i_allocval0 1 "Interrupt allocation 0 valid"; 190 _ 24 rsvd; 191 }; 192 193 // 8.3.5.2.9 194 // XXX: Not sure if this is correct... 195 regarray vfrscint rw addr(base, 0x00180) [2] "VF RSC Enable Interrupt" type(uint32); 196 197 // 8.3.5.2.10 198 register vfpbacl rw1c addr(base, 0x00148) "VF MSI-X PBA Clear" { 199 penbit 3 "MSI-X Pending Bits Clear. Reading returns PBA vector."; 200 _ 29 rsvd; 201 }; 202 203 /************************************ 204 * 8.3.5.3 Receive DMA Registers -- VF 205 ***********************************/ 206 207 // 8.3.5.3.1 208 regarray vfrdbal rw addr(base, 0x01000) [8; 0x40] 209 "VF Receive Descriptor Base Address Low (#0-#7)" 210 type(uint32); 211 212 // 8.3.5.3.2 213 regarray vfrdbah rw addr(base, 0x01004) [8; 0x40] 214 "VF Receive Descriptor Base Address High (#0-#7)" 215 type(uint32); 216 217 // 8.3.5.3.3 218 regarray vfrdlen rw addr(base, 0x01008) [8; 0x40] 219 "VF Receive Descriptor Length (#0-#7)" 220 type(uint32); 221 222 // 8.3.5.3.4 223 regarray vfrdh rw addr(base, 0x01010) [8; 0x40] 224 "VF Receive Descriptor Head (#0-#7)" 225 type(uint32); 226 227 // 8.3.5.3.5 228 regarray vfrdt rw addr(base, 0x01018) [8; 0x40] 229 "VF Receive Descriptor Tail (#0-#7)" 230 type(uint32); 231 232 // 8.3.5.3.6 233 regtype rxdctl "Receive Descriptor Control" { 234 _ 25 rsvd; 235 enable 1 "Receive Queue Enable"; 236 _ 4 rsvd; 237 vme 1 "VLAN Mode Enable"; 238 _ 1 rsvd; 239 }; 240 241 regarray vfrxdctl rw addr(base, 0x01028) [8; 0x40] 242 "VF Receive Descriptor Control (#0-#7)" 243 type(rxdctl); 244 245 // 8.3.5.3.7 246 constants rx_desctype "RX Descriptor Type" { 247 legacy = 0b000 "Legacy"; 248 adv_1buf = 0b001 "Advanced descriptor one buffer"; 249 adv_hdrsp = 0b010 "Advanced descriptor header splitting"; 250 adv_usehb = 0b101 "Advanced descriptor header splitting always use header buffer"; 251 }; 252 253 regtype srrctl "Split Receive Control Registers" { 254 bsz_pkt 5 "Receive Buffer Size for Packet Buffer"; 255 _ 3 mbz; 256 bsz_hdr 6 "Receive Buffer Size for Header Buffer"; 257 _ 8 rsvd; 258 rdmts 3 "Receive Descriptor Minimum Threshold Size"; 259 desctype 3 type(rx_desctype) "Define the descriptor type"; 260 drop_en 1 "Drop Enabled"; 261 _ 3 rsvd; 262 }; 263 264 regarray vfsrrctl rw addr(base, 0x01014) [8; 0x40] 265 "VF Split Receive Control Registers (#0-#7)" 266 type(srrctl); 267 268 // 8.3.5.3.8 269 register vfpsrtype rw addr(base, 0x00300) "VF Replication Packet Split Receive Type" { 270 _ 1 mbz; 271 split_nfs 1 "Split received NFS packets after NFS header"; 272 _ 2 mbz; 273 split_tcp 1 "Split received TCP packets after TCP header"; 274 split_udp 1 "Split received UDP packets after UDP header"; 275 _ 2 mbz; 276 split_ip4 1 "Split received IPv4 packets after IPv4 header"; 277 split_ip6 1 "Split received IPv6 packets after IPv6 header"; 278 _ 2 mbz; 279 split_l2 1 "Split received L2 packets after L2 header"; 280 _ 16 mbz; 281 rqpl 3 "Number of bits to use for RSS redirection"; 282 }; 283 284 // 8.3.5.3.9 285 constants rsc_maxdesc "Maximum descriptors per Large receive" { 286 max_1desc = 0b00 "Maximum of 1 descriptor per large receive"; 287 max_4desc = 0b01 "Maximum of 4 descriptors per large receive"; 288 max_8desc = 0b10 "Maximum of 8 descriptors per large receive"; 289 max_16desc = 0b11 "Maximum of 16 descriptors per large receive"; 290 }; 291 292 regtype rscctl "RSC Control" { 293 rsc_en 1 "RSC Enable"; 294 _ 1 rsvd; 295 maxdesc 2 type(rsc_maxdesc) "Maximum descriptors per Large receive"; 296 _ 28 rsvd; 297 }; 298 299 regarray vfrscctl rw addr(base, 0x0102c) [8; 0x40] 300 "RSC Control (#0-#7)" 301 type(rscctl); 302 303 /************************************ 304 * 8.3.5.4 Transmit Registers -- VF 305 ***********************************/ 306 307 // 8.3.5.4.1 308 regarray vftdbal rw addr(base, 0x02000) [4; 0x40] 309 "VF Transmit Descriptor Base Address Low" 310 type(uint32); 311 312 // 8.3.5.4.2 313 regarray vftdbah rw addr(base, 0x02004) [4; 0x40] 314 "VF Transmit Descriptor Base Address High" 315 type(uint32); 316 317 // 8.3.5.4.3 318 regarray vftdlen rw addr(base, 0x02008) [4; 0x40] 319 "VF Transmit Descriptor Length" 320 type(uint32); 321 322 // 8.3.5.4.4 323 // rw is only partially accurate here. This register must only be written 324 // directly after reset. 325 regarray vftdh rw addr(base, 0x02010) [4; 0x40] 326 "VF Transmit Descriptor Head" 327 type(uint32); 328 329 // 8.3.5.4.5 330 regarray vftdt rw addr(base, 0x02018) [4; 0x40] 331 "VF Transmit Descriptor Tail" 332 type(uint32); 333 334 // 8.3.5.4.6 335 regarray vftxdctl rw addr(base, 0x02028) [4; 0x40] "VF Transmit Descriptor Control" { 336 pthresh 7 "Pre-Fetch Threshold"; 337 _ 1 rsvd; 338 hthresh 7 "Host Threshold"; 339 _ 1 rsvd; 340 wthresh 7 "Write-Back Threshold"; 341 _ 2 rsvd; 342 enable 1 "Transmit Queue Enable"; 343 swflsh 1 "Transmit Software Flush"; 344 _ 5 rsvd; 345 }; 346 347 // 8.3.5.4.7 348 regarray vftdwbal rw addr(base, 0x02038) [4; 0x40] "VF Tx Descriptor Completion Write Back Address Low" { 349 headwb_en 1 "Head Write-Back Enable"; 350 _ 1 rsvd; 351 headwb_low 30 "Lowest 32 bits of the head write-back memory location"; 352 }; 353 354 // 8.3.5.4.8 355 regarray vftdwbah rw addr(base, 0x0203c) [4; 0x40] "VF Tx Descriptor Completion Write Back Address High" { 356 headwb_high 32 "Highest 32 bits of the head write-back memory location"; 357 }; 358 359 /************************************ 360 * 8.3.5.5 DCA Registers -- VF 361 ***********************************/ 362 363 // 8.3.5.5.1 364 regtype dca_rxctrl "Rx DCA Control Register" { 365 _ 5 rsvd; 366 rxdca_desc 1 "Descriptor DCA EN"; 367 rxdca_hdr 1 "Rx Header DCA EN"; 368 rxdca_payl 1 "Payload DCA EN"; 369 _ 1 rsvd; 370 rxdesc_rdro 1 "Rx Descriptor Read Relax Order Enable"; 371 _ 1 rsvd; 372 rxdesc_wbro 1 mbz "Rx Descriptor Write Back Relax Order Enable"; 373 _ 1 rsvd; 374 rxdata_wrro 1 "Rx data Write Relax Order Enable"; 375 _ 1 rsvd; 376 rxhdr_ro 1 "Rx Split Header Relax Order Enable"; 377 _ 8 rsvd; 378 cpuid 8 "Physical ID"; 379 }; 380 381 regarray vfdca_rxctrl rw addr(base, 0x0100c) [8; 0x40] 382 "VF Rx DCA Control Register (#0-#7)" 383 type(dca_rxctrl); 384 385 // 8.3.5.5.2 386 regarray vfdca_txctrl rw addr(base, 0x0200c) [8; 0x40] "VF Tx DCA Control Registers" { 387 _ 5 rsvd; 388 txdesc_dca 1 "Descriptor DCA Enable"; 389 _ 3 rsvd; 390 txdesc_rdro 1 "Tx Descriptor Read Relax Order Enable"; 391 _ 1 rsvd; 392 txdesc_wbro 1 "Relax Order Enable of Tx Descriptor well as head pointer write back"; 393 _ 1 rsvd; 394 txdata_rdro 1 "Tx Data Read Relax Order Enable"; 395 _ 10 rsvd; 396 cpuid 8 "Physical ID"; 397 }; 398 399 /************************************ 400 * 8.3.5.6 Statistics -- VF 401 ***********************************/ 402 403 // 8.3.5.6.1 404 register vfgprc ro addr(base, 0x0101c) "VF Good packets received count" 405 type(uint32); 406 407 // 8.3.5.6.2 408 register vfgptc ro addr(base, 0x0201c) "VF Good packets trasmitted count" 409 type(uint32); 410 411 // 8.3.5.6.3 412 register vfgorc_lsb ro addr(base, 0x01020) "VF Good Octets Received Count Low" 413 type(uint32); 414 415 // 8.3.5.6.4 416 register vfgorc_msb ro addr(base, 0x01024) "VF Good Octets Received Count High" 417 type(uint32); 418 419 // 8.3.5.6.5 420 register vfgotc_lsb ro addr(base, 0x02020) "VF Good Octets Transmitted Count Low" 421 type(uint32); 422 423 // 8.3.5.6.6 424 register vfgotc_msb ro addr(base, 0x02024) "VF Good Octets Transmitted Count High" 425 type(uint32); 426 427 // 8.3.5.6.7 428 register vfmprc ro addr(base, 0x01034) "VF Multicast Packets Received Count" 429 type(uint32); 430}; 431