1/* 2 * Copyright (c) 2015, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * cpuid_amd.dev 11 * 12 * DESCRIPTION: ia32 CPU ID instruction results 13 * 14 * See 15 * AMD CPUID Specification, Rev. 2.28, Pub.#25481, April 2008 16 */ 17 18device cpuid_amd lsbfirst () "ia32 / Intel64 CPUID instruction results" { 19 20 /* 21 *============================================================================ 22 * Basic Information. 23 *============================================================================ 24 */ 25 26 /* 27 * CPUID(0, _) 28 * --------------------------------------------------------------------------- 29 */ 30 datatype basic lsbfirst (32) "" { 31 max_cpuid 32 rw "Maximum Input Value for Basic CPUID Information"; 32 vendor0 32 rw "Vendor string part 1"; 33 vendor2 32 rw "Vendor string part 3"; 34 vendor1 32 rw "Vendor string part 2"; 35 }; 36 37 /* 38 * CPUID(1, _) 39 * --------------------------------------------------------------------------- 40 */ 41 42 datatype family lsbfirst(32) "family information in eax register" { 43 stepping 4 rw "Processor Stepping ID"; 44 model 4 rw "Processor Model"; 45 family 4 rw "Processor Family"; 46 _ 4 mbz "Reserved"; 47 extmodel 4 rw "Extended Model ID"; 48 extfamily 8 rw "Extended Family ID"; 49 _ 4 mbz "Reserved"; 50 }; 51 52 datatype miscinfo lsbfirst(32) "info returned in ebx register" { 53 brand_idx 8 rw "Brand index"; 54 cflush_sz 8 rw "CLFLUSH line size (Value * 8 = cache line size in bytes)"; 55 max_log_proc 8 rw "LogicalProcessorCount is the number of cores per processor"; 56 init_apicid 8 rw "Initial APIC ID"; 57 }; 58 59 datatype features lsbfirst(32) "features returned in {ecx, edx}" { 60 /* Feature Information (see Figure 3-6 and Table 3-19) */ 61 sse3 1 rw "Streaming SIMD Extensions 3 (SSE3). "; 62 pclmulqdq 1 rw "PCLMULQDQ."; 63 dtes64 1 rw "64-bit DS Area"; 64 monitor 1 rw "MONITOR/MWAIT"; 65 ds_cpl 1 rw "CPL Qualified Debug Store. "; 66 vmx 1 rw "Virtual Machine Extensions"; 67 smx 1 rw "Safer Mode Extensions. "; 68 eist 1 rw "Enhanced Intel SpeedStep(r) technology. "; 69 tm2 1 rw "Thermal Monitor 2"; 70 ssse3 1 rw "Supplemental Streaming SIMD Extensions 3 (SSSE3)"; 71 cntx_id 1 rw "L1 Context ID. A"; 72 sdbg 1 rw "IA32_DEBUG_INTERFACE MSR "; 73 fma 1 rw "FMA extensions using YMM state."; 74 cmpxchg16b 1 rw "CMPXCHG16B Available"; 75 xtpr 1 rw "xTPR Update Control"; 76 pdcm 1 rw "Perfmon and Debug Capability"; 77 _ 1 mbz ""; 78 pcid 1 rw "Process-context identifiers"; 79 dca 1 rw "ability to prefetch data from a memory mapped device."; 80 sse4_1 1 rw "supports SSE4.1. "; 81 sse4_2 1 rw "supports SSE4.2. "; 82 x2apic 1 rw "supports x2APIC feature"; 83 movbe 1 rw "supports MOVBE instruction"; 84 popcnt 1 rw "supports the POPCNT instruction."; 85 tsc_one 1 rw "local APIC timer supports one-shot operation "; 86 aesni 1 rw " AESNI instruction extensions"; 87 xsave 1 rw " XSAVE/XRSTOR processor "; 88 osxsave 1 rw "OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV instruction"; 89 avx 1 rw "AVX instruction extensions"; 90 f16c 1 rw "16-bit floating-point conversion instructions."; 91 rdrand 1 rw "supports RDRAND instruction."; 92 _ 1 mbz ""; 93 94 /* Feature Information (see Figure 3-7 and Table 3-20) */ 95 fpu 1 rw "Floating Point Unit On-Chip"; 96 vme 1 rw "Virtual 8086 Mode Enhancements"; 97 de 1 rw "Debugging Extensions. "; 98 pse 1 rw "Page Size Extension"; 99 tsc 1 rw "Time Stamp Counter."; 100 msr 1 rw "Model Specific Registers RDMSR and WRMSR Instructions"; 101 pae 1 rw "Physical Address Extension"; 102 mce 1 rw "Machine Check Exception. "; 103 cx8 1 rw "CMPXCHG8B Instruction."; 104 apic 1 rw "APIC On-Chip. "; 105 _ 1 mbz ""; 106 sep 1 rw "SYSENTER and SYSEXIT Instructions."; 107 mtrr 1 rw "Memory Type Range Registers"; 108 pge 1 rw "Page Global Bit"; 109 mca 1 rw "Machine Check Architecture."; 110 cmov 1 rw "Conditional Move Instructions"; 111 pat 1 rw "Page Attribute Table"; 112 pse36 1 rw "36-Bit Page Size Extension"; 113 psn 1 rw "Processor Serial Number. "; 114 clfsh 1 rw "CLFLUSH Instruction"; 115 _ 1 rw ""; 116 ds 1 rw "Debug Store"; 117 acpi 1 rw "Thermal Monitor and Software Controlled Clock Facilities"; 118 mmx 1 rw "Intel MMX Technology"; 119 fxsr 1 rw "FXSAVE and FXRSTOR Instructions"; 120 sse 1 rw "SSE1"; 121 sse2 1 rw "SSE2"; 122 ss 1 rw "Self Snoop"; 123 htt 1 rw "Max APIC IDs reserved field is Valid"; 124 tm 1 rw "Thermal Monitor"; 125 _ 1 mbz ""; 126 pbe 1 rw "Pending Break Enable. "; 127 }; 128 129 /* 130 * CPUID(0x80000008, _) 131 * --------------------------------------------------------------------------- 132 */ 133 datatype addrspace lsbfirst(32) " Long Mode Address Size Identifiers (eax)" { 134 physical 8 rw "Maximum physical byte address size in bits"; 135 linear 8 rw "Maximum linear byte address size in bits. "; 136 guest 8 rw " maximum guest physical byte address size in bits"; 137 _ 8 mbz "reserved"; 138 }; 139 140 datatype apicid lsbfirst(32) "APIC ID Size and Core Count (ecx)" { 141 ncores 8 rw "number of physical cores - 1"; 142 _ 4 mbz "Reserved"; 143 apic_sz 4 rw "APIC ID size"; 144 _ 16 mbz "reserved"; 145 }; 146 147 /* 148 * CPUID(0x80000005, _) L1 Cache and TLB Identifiers 149 * --------------------------------------------------------------------------- 150 */ 151 datatype tlb_l1 lsbfirst(32) "" { 152 itlb_sz 8 rw "L2 instruction TLB number of entries for 2/4MB pages "; 153 itlb_assoc 8 rw "L2 instruction TLB associativity for 2/4MB pages "; 154 dtlb_sz 8 rw "L2 data TLB number of entries for 2/4MB pages "; 155 dtlb_assoc 8 rw "L2 data TLB associativity for 2/4MB pages"; 156 }; 157 158 datatype l1_2m_tlb lsbfirst(32) "Fn8000_0005_EAX L1 Cache and TLB Identifiers" { 159 itlb_sz 8 rw "L2 instruction TLB number of entries for 2/4MB pages "; 160 itlb_assoc 8 rw "L2 instruction TLB associativity for 2/4MB pages "; 161 dtlb_sz 8 rw "L2 data TLB number of entries for 2/4MB pages "; 162 dtlb_assoc 8 rw "L2 data TLB associativity for 2/4MB pages"; 163 }; 164 165 datatype l1_4k_tlb lsbfirst(32) "Fn8000_0005_EBX L1 Cache and TLB Identifiers" { 166 itlb_sz 8 rw "L2 instruction TLB number of entries for 4 KB pages. "; 167 itlb_assoc 8 rw "L2 instruction TLB associativity for 4 KB pages "; 168 dtlb_sz 8 rw "L2 data TLB number of entries for 4 KB pages "; 169 dtlb_assoc 8 rw "L2 data TLB associativity for 4 KB pages"; 170 }; 171 172 datatype l1_dcache lsbfirst(32) " Fn8000_0005_ECX L1 Cache and TLB Identifiers" { 173 linesize 8 rw "L1 cache line size in bytes. "; 174 lines_per_tag 8 rw "L1 cache lines per tag. "; 175 assoc 8 rw "L1 cache associativity. See Table 4."; 176 size 8 rw "L1 cache size in KB."; 177 }; 178 179 datatype l1_icache lsbfirst(32) "Fn8000_0005_EDX L1 Cache and TLB Identifiers" { 180 linesize 8 rw "L1 cache line size in bytes. "; 181 lines_per_tag 8 rw "L1 cache lines per tag. "; 182 assoc 8 rw "L1 cache associativity. See Table 4."; 183 size 8 rw "L1 cache size in KB."; 184 }; 185 186 /* 187 * CPUID(0x80000006, _) TLB and L2/L3 cache information 188 * --------------------------------------------------------------------------- 189 */ 190 191 constants cache_assoc "AMD cache associativity values" { 192 cache_assoc_disabled = 0x0 ""; 193 cache_assoc_direct = 0x1 ""; 194 cache_assoc_2way = 0x2 ""; 195 cache_assoc_4way = 0x4 ""; 196 cache_assoc_8way = 0x6 ""; 197 cache_assoc_16way = 0x8 ""; 198 cache_assoc_32way = 0xa ""; 199 cache_assoc_48way = 0xb ""; 200 cache_assoc_64way = 0xc ""; 201 cache_assoc_96way = 0xd ""; 202 cache_assoc_128way = 0xe ""; 203 cache_assoc_fully = 0xf ""; 204 }; 205 206 datatype tlb_l2 lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" { 207 itlb_sz 12 rw "L2 instruction TLB number of entries for 2/4MB pages "; 208 itlb_assoc 4 rw "L2 instruction TLB associativity for 2/4MB pages "; 209 dtlb_sz 12 rw "L2 data TLB number of entries for 2/4MB pages "; 210 dtlb_assoc 4 rw "L2 data TLB associativity for 2/4MB pages"; 211 }; 212 213 datatype l2_2m_tlb lsbfirst(32) "Fn8000_0006_EAX L2 TLB Identifiers" { 214 itlb_sz 12 rw "L2 instruction TLB number of entries for 2/4MB pages "; 215 itlb_assoc 4 rw "L2 instruction TLB associativity for 2/4MB pages "; 216 dtlb_sz 12 rw "L2 data TLB number of entries for 2/4MB pages "; 217 dtlb_assoc 4 rw "L2 data TLB associativity for 2/4MB pages"; 218 }; 219 220 datatype l2_4k_tlb lsbfirst(32) " Fn8000_0006_EBX L2 TLB Identifiers" { 221 itlb_sz 12 rw "L2 instruction TLB number of entries for 4 KB pages. "; 222 itlb_assoc 4 rw "L2 instruction TLB associativity for 4 KB pages "; 223 dtlb_sz 12 rw "L2 data TLB number of entries for 4 KB pages "; 224 dtlb_assoc 4 rw "L2 data TLB associativity for 4 KB pages"; 225 }; 226 227 datatype l2_cache lsbfirst(32) "Fn8000_0006_ECX L2 Cache Identifiers" { 228 linesize 8 rw "L2 cache line size in bytes. "; 229 lines_per_tag 4 rw "L2 cache lines per tag. "; 230 assoc 4 rw "L2 cache associativity. See Table 4."; 231 size 16 rw "L2 cache size in KB."; 232 }; 233 234 235 datatype l3_cache lsbfirst(32) "Fn8000_0006_EDX L3 Cache Identifiers" { 236 linesize 8 rw "L3 cache line size in bytes. "; 237 lines_per_tag 4 rw "L3 cache lines per tag. "; 238 assoc 4 rw "L3 cache associativity. See Table 4."; 239 _ 2 mbz "Reserved"; 240 size 14 rw "Specifies the L3 cache size in 512kb blocks"; 241 }; 242 243 /* 244 * CPUID(0x80000019, _) TLB for 1G Pages 245 * --------------------------------------------------------------------------- 246 */ 247 datatype tlb_1g_l1 lsbfirst(32) "TLB 1GB Page Identifiers eax" { 248 itlb_sz 12 "L1 instruction TLB number of entries for 1 GB pages"; 249 itlb_assoc 4 "L1 instruction TLB associativity for 1 GB pages. See Table 4"; 250 dtlb_sz 12 "L1 data TLB number of entries for 1 GB pages"; 251 dtlb_assoc 4 "L1 data TLB associativity for 1 GB pages. See Table 4."; 252 }; 253 254 datatype tlb_1g_l2 lsbfirst(32) "TLB 1GB Page Identifiers ebx" { 255 itlb_sz 12 "L2 instruction TLB number of entries for 1 GB pages"; 256 itlb_assoc 4 "L2 instruction TLB associativity for 1 GB pages. See Table 4"; 257 dtlb_sz 12 "L2 data TLB number of entries for 1 GB pages"; 258 dtlb_assoc 4 "L2 data TLB associativity for 1 GB pages. See Table 4."; 259 }; 260 261 /* 262 * CPUID(0x8000001D, _) 263 * --------------------------------------------------------------------------- 264 */ 265 constants cache_type "AMD Cache Type values" { 266 cache_type_null = 0x0 "No more caches"; 267 cache_type_data = 0x1 "data cache"; 268 cache_type_instr = 0x2 "Instruction Cache"; 269 cache_type_unified = 0x3 "Unified Cache"; 270 }; 271 272 /* EAX */ 273 datatype cache_info_eax lsbfirst (32) "" { 274 ctype 5 "Cache Type Field"; 275 level 3 "Cache Level (starts at 1)"; 276 selfinit 1 "Self Initializing cache level (does not need SW initialization)"; 277 fullyassoc 1 "Fully Associative cache"; 278 _ 4 "Reserved"; 279 num_sharing 12 "number of cores sharing cache - 1"; 280 _ 6 ""; 281 }; 282 283 datatype cache_info_ebx lsbfirst (32) "" { 284 cachelinesize 12 "cache line size in bytes - 1"; 285 partitions 10 "cache physical line partitions - 1"; 286 assoc 10 "cache number of ways - 1"; 287 }; 288 289 datatype cache_info_ecx lsbfirst (32) "" { 290 num_sets 32 "The number of Sets - 1"; 291 }; 292 293 datatype cache_info_edx lsbfirst (32) "" { 294 wb_inv 1 "Write-Back Invalidate/Invalidate"; 295 inclusive 1 "Cache Inclusiveness"; 296 _ 30 "reserved"; 297 }; 298 299 /* 300 * CPUID(0x8000001E, _) topology extensions 301 * --------------------------------------------------------------------------- 302 */ 303 datatype ext_apic lsbfirst (32) "register eax" { 304 extended_apicid 32 "extended APIC ID"; 305 }; 306 307 datatype cuid lsbfirst (32) "Fn8000_001E_EBX Compute Unit Identifiers" { 308 cuid 8 "compute unit id"; 309 ncores 2 "Number of cores per compute unit - 1"; 310 _ 22 "Reserved"; 311 }; 312 313 datatype nid lsbfirst (32) "Fn8000_001E_ECX Node Identifiers" { 314 nodeid 8 "Specifies the node ID"; 315 nnodeds 3 "Number of nodes per processor - 1"; 316 _ 21 "Reserved"; 317 }; 318}; 319 320 321 322 323 324 325 326