1/* 2 * Copyright (c) 2012, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * cortex_a9_pit.dev 11 * 12 * DESCRIPTION: Cortex A9 Private Timer and watchdog 13 * 14 * This is derived from: 15 * 16 * Cortex-A9 MPCore Technical Reference Manual 17 * (DDI0407G_cortex_a9_mpcore_r3p0_trm.pdf) 18 * 19 * This implements private timers and watchdogs 20 */ 21 22 device cortex_a9_pit msbfirst ( addr base ) "Cortex A9 Private Timer and watchdog" { 23 24 register TimerLoad addr(base, 0x0) "Private Timer Load Register" type(uint32); 25 26 register TimerCounter addr(base, 0x4) "Private Timer Counter Register" type(uint32); 27 28 register TimerControl addr(base, 0x8) "Private Timer Control Register" { 29 _ 16 mbz; 30 prescale 8 rw "Prescale factor"; 31 _ 5 mbz; 32 int_enable 1 rw "Interrupt enable bit"; 33 auto_reload 1 rw "Single shot or reload mode"; 34 timer_enable 1 rw "Timer enable bit"; 35 }; 36 37 register TimerIntStat addr(base, 0xc) "Private Timer Interrupt Status Register" { 38 _ 31 mbz; 39 event_flag 1 rw1c; 40 }; 41 42 register WatchdogLoad addr(base, 0x20) "Watchdog Load Register" type(uint32); 43 44 register WatchdogCounter addr(base, 0x24) "Watchdog Counter Register" type(uint32); 45 46 register WatchdogControl addr(base, 0x28) "Watchdog Control Register" { 47 _ 16 mbz; 48 prescale 8 rw "Prescale factor"; 49 _ 4 mbz; 50 wd_mode 1 rw "Selects Watchdog or Timer mode"; 51 int_enable 1 rw "Interrupt enable bit"; 52 auto_reload 1 rw "Single shot or reload mode"; 53 wd_enable 1 rw "Timer enable bit"; 54 }; 55 56 register WatchdogIntStat addr(base, 0x2c) "Watchdog Interrupt Status Register" { 57 _ 31 mbz; 58 event_flag 1 rw1c; 59 }; 60 61 register WatchdogResStat addr(base, 0x30) "Watchdog Reset Status Register" { 62 _ 31 mbz; 63 reset_flag 1 rw1c; 64 }; 65 66 // Write 0x12345678 then 0x87654321 to this register to disable watchdog mode 67 register WatchdogDisable wo addr(base, 0x34) "Watchdog Disable Register" type(uint32); 68 69 70 }; 71