1/*
2 * Copyright (c) 2009, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * arm_icp_pit.dev
11 *
12 * DESCRIPTION: Timers for for integrator/cp
13 *
14 * This is derived from:
15 *
16 * Integrator/CP User Guide
17 * (DUI0159B_integratorcp_1_0_ug.pdf)
18 *
19 */
20
21device arm_icp_pit msbfirst ( addr base ) "ARM Integrator timer"
22{
23  constants scale "Timer scaling factors" {
24    none   = 0b00 "none";
25    div16  = 0b01 "divide by 16";
26    div256 = 0b10 "divide by 256";
27  };
28
29  constants mode "Timer Mode" {
30    free   = 0b0 "Counts once and then wraps to 0xffff";
31    reload = 0b1 "Reloads from load register at end of each count"; 
32  };
33
34  register LOAD         addr(base, 0x00) "Load value for timer" {
35     value     32 rw;
36  };
37
38  register CURRENT      addr(base, 0x04) "Current value for timer" {
39     value     32 ro;
40  };
41
42  register CONTROL      addr(base, 0x08) "Control register" {
43     _         24;
44     enable     1   rw;
45     mode       1   rw type(mode);
46     int_enable 1   rw;
47     _          1;
48     prescale   2   rw type(scale);
49     timer32    1   rw "Timer 32-bit (otherwise 16-bit)";
50     oneshot    1   rw "Stop rather than wrap.";
51  };
52
53  register INTCLR       addr(base, 0x0c) "Interrupt clear" {
54     value     32   wo;
55  };
56
57  register RIS          addr(base, 0x10) "Raw interrupt status" {
58     _         31;
59     status     1   ro   "Raw status";
60  };
61
62  register MIS          addr(base, 0x14) "Masked interrupt status" {
63     _         31;
64     status     1   ro  "Masked status";
65  };
66
67  register BGLOAD       addr(base, 0x18) "Background load value for timer" {
68     value     32   rw  "Reload value for periodic timer, does not affect CURRENT";
69  };
70};
71
72