1/* 2 * Copyright (c) 2009, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * arm_icp_pic0.dev 11 * 12 * DESCRIPTION: Primary interrupt controller for integrator/cp 13 * 14 * This is derived from: 15 * 16 * Integrator/CP User Guide 17 * (DUI0159B_integratorcp_1_0_ug.pdf) 18 * 19 */ 20 21device arm_icp_pic0 msbfirst ( addr base ) "ARM Integrator Primary PIC" 22{ 23 regtype source "Interrupt controller sources" { 24 _ 3; 25 TS_PENINT 1 "Touchscreen pen-down event interrupt"; 26 ETH_INT 1 "Ethernet interface interrupt"; 27 CPPLDINT 1 "Interrupt from secondary interrupt controller"; 28 AACIINT 1 "Audio interface interrupt"; 29 MMCIINT1 1 "MultiMedia card interface 1"; 30 MMCIINT0 1 "MultiMedia card interface 0"; 31 CLCDCINT 1 "Display controller interrupt"; 32 _ 11; 33 LM_LLINT1 1 "Logic module low-latency interrupt 1"; 34 LM_LLINT0 1 "Logic module low-latency interrupt 0"; 35 RTCINT 1 "Real time clock interrupt"; 36 TIMERINT2 1 "Counter-timer 2 interrupt"; 37 TIMERINT1 1 "Counter-timer 1 interrupt"; 38 TIMERINT0 1 "Counter-timer 0 interrupt"; 39 MOUSEINT 1 "Mouse interrupt"; 40 KBDINT 1 "Keyboard interrupt"; 41 UARTINT1 1 "UART 1 interrupt"; 42 UARTINT0 1 "UART 0 interrupt"; 43 SOFTINT 1 "Software interrupt"; 44 }; 45 46 register PIC_IRQ_STATUS ro addr (base, 0x00) "IRQ gated interrupt status" 47 type(source); 48 49 register PIC_IRQ_RAWSTAT ro addr (base, 0x04) "IRQ raw interrupt status" 50 type(source); 51 52 register PIC_IRQ_ENABLESET rw addr (base, 0x08) "IRQ enable set" 53 type(source); 54 55 register PIC_IRQ_ENABLECLR wo addr (base, 0x0c) "IRQ enable clear" 56 type(source); 57 58 register PIC_INT_SOFTSET rw addr (base, 0x10) "Software interrupt set" 59 type(source); 60 61 register PIC_INT_SOFTCLR wo addr (base, 0x14) "Software interrupt clear" 62 type(source); 63 64 register PIC_FIQ_STATUS ro addr (base, 0x20) "FIQ gated interrupt status" 65 type(source); 66 67 register PIC_FIQ_RAWSTAT ro addr (base, 0x24) "FIQ raw interrupt status" 68 type(source); 69 70 register PIC_FIQ_ENABLESET rw addr (base, 0x28) "FIQ enable set" 71 type(source); 72 73 register PIC_FIQ_ENABLECLR wo addr (base, 0x2c) "FIQ enable clear" 74 type(source); 75}; 76