1/*
2 * Copyright (c) 2015, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * apm88xxxx/apm88xxxx_pc16550.dev
11 *
12 * DESCRIPTION: APM88xxxx PC16550 UART
13 *
14 * This is derived from:
15 *
16 * APM88xx0x Processor Family Register Reference -- Volume 1
17 * Document Issue 0.98 (APM 2012-0052-1)
18 *
19 * This file only incorporates the parts relevant for UART operation.
20 * Registers relevant for IrDA, CIR, and other modes are not yet
21 * described. 
22 */
23device apm88xxxx_pc16550 msbfirst (addr base) "APM88xxxx UART" {
24
25    constants data_len "Data Length" {
26        bits5   = 0b00   "5 Bits";
27        bits6   = 0b01   "6 Bits";
28        bits7   = 0b10   "7 Bits";
29        bits8   = 0b11   "8 Bits";
30    };
31
32    register RBR ro addr (base, 0x0) "Receive Buffer" {
33        _       24;
34        rbr     8 ro        "Receive buffer register";
35    };
36
37    register THR wo also addr (base, 0x0) "Transmit Register" {
38        _       24;
39        thr     8 wo        "Transmit register";
40    };
41
42    register IIR ro addr (base, 0x8) "Interrupt Identity" type(uint32);
43
44    register lcr rw addr (base, 0xc) "Line control" {
45        _       24;
46        dlab    1           "Divisor latch access bit";
47        bc      1           "Break control bit";
48        sp      1 rsvd      "Stick parity";
49        eps     1           "Even parity select";
50        pen     1           "Parity enable";
51        stop    1           "stop bit";
52        dls     2 type(data_len) "Data length select";
53    };
54
55    register LSR ro addr (base, 0x14) "Line Status" {
56        _       24;
57        rfe      1          "Receive FIFO error";
58        temt     1          "Transmitter empty";
59        thre     1          "Transmit holding register empty";
60        bi       1          "Break interrupt";
61        fe       1          "Framing error";
62        pe       1          "Parity error";
63        oe       1          "Overrun error";
64        dr       1          "Data ready";
65    };
66
67
68};
69