1/*
2 * Copyright (c) 2009, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * ahci_hba.dev
11 *
12 * DESCRIPTION: AHCI (SATA) Host bus adaptor, generic registers (ports
13 *              have their own devive definition. 
14 * 
15 * Section numbers refer to the Serial ATA Advanced Host Controller
16 *   Interface (AHCI) specification 1.3, June 2008
17 */
18
19device ahci_hba msbfirst (addr b) "AHCI generic" {
20
21    // 3.1.1
22    
23    constants speed "Interface speed" {
24	gen1	= 0b0001 "Gen 1 (1.5 Gbps)";
25	gen2	= 0b0010 "Gen 2 (3 Gbps)";
26	gen3	= 0b0011 "Gen 3 (6 Gbps)";
27    };
28
29    register cap ro addr(b,0x00) "HBA capabilities" {
30	s64a	1 "Supports 64-bit addressing";
31	sncq	1 "Supports native command queueing";
32	ssntf	1 "Supports SNotification register";
33	smps	1 "Supports mechanical presence switch";
34	sss	1 "Supports staggered spin-up";
35	salp	1 "Supports aggressive link power management";
36	sal	1 "Supports activity LED";
37	sclo	1 "Supports command list override";
38	iss	4 type(speed) "Interface speed support";
39	_	1 rsvd;
40	sam	1 "Supports AHCI mode only";
41	spm	1 "Supports port multiplier";
42	fbss	1 "FIS-based switching supported";
43	pmd	1 "PIO multiple DRQ block";
44	ssc	1 "Slumber state capable";
45	psc	1 "Partial state capable";
46	ncs	5 "Number of command slots";
47	cccs	1 "Command completion coalescing supported";
48	ems	1 "Enclosure management supported";
49	sxs	1 "Supports external SATA";
50	np	5 "Number of ports";
51    };
52    
53    // 3.1.2
54    register ghc rw addr(b,0x04) "Global HBA control" {
55	ae	1 rw "AHCI enable";
56	_	28 rsvd;
57	mrsm	1 ro "MSI revert to single message";
58	ie	1 rw "Interrupt enable";
59	hr	1 rw "HBA reset";
60    };
61    
62    // 3.1.3
63    register is rwc addr(b,0x08) "Interrupt status" type(uint32);
64    
65    // 3.1.4
66    register pi ro addr(b,0x0c) "Ports implemented" type(uint32);
67    
68    // 3.1.5 
69    register vs ro addr(b,0x10) "AHCI version" {
70	major	16 "Major version";
71	minor	16 "Minor version";
72    };
73    
74    // 3.1.6
75    register ccc_ctl rw addr(b,0x14) "Command completion coalescing control" {
76	tv	16 "Timeout value";
77	cc	8 "Command completions";
78	intr	5 ro "Interrupt";
79	_	2 rsvd;
80	en	1 "Enable";
81    };
82    
83    // 3.1.7
84    register ccc_ports rw addr(b,0x18) "Command completions coalescing ports"
85	type(uint32);
86
87    // 3.1.8 
88    register em_loc ro addr(b,0x1c) "Enclosure management location" {
89	ofst	16 "Offset";
90	sz	16 "Bufer size";
91    };
92    
93    // 3.1.9
94    register em_ctl addr(b,0x20) "Enclosure management control" {
95	_	4 rsvd;
96	pm	1 ro "Port multiplier support";
97	alhd	1 ro "Activity LED hardware driven";
98	xmt	1 ro "Transmit only";
99	smb	1 ro "Single message buffer";
100	_	4 rsvd;
101	sgpio	1 ro "SGPIO enclosure management messages";
102	ses2	1 ro "SES-2 enclosure management messages";
103	safte	1 ro "SAF-TE enclosure management messages";
104	led	1 ro "LED message types";
105	_	6 rsvd;
106	rst	1 rw "Reset";
107	tm	1 rw "Transmit message";
108	_	7 rsvd;
109	mr	1 rw1c "Message received";
110    };
111
112    // 3.1.10 
113    register cap2 ro addr(b,0x24) "HBA capabilities extended" {
114	_	29 rsvd;
115	apst	1 "Automatic partial to slumber transitions";
116	nvmp	1 "NVMHCI present";
117	boh	1 "BIOS/OS handoff";
118    };
119    
120    // 3.1.11
121    register bohc addr(b,0x28) "BIOS/OS handoff control and status" {
122	_	27 rsvd;
123	bb	1 rw "BIOS busy";
124	ooc	1 rw1c "OS ownership change";
125	sooe	1 rw "SMI on OS ownership change enable";
126	oos	1 rw "OS owned semaphore";
127	bos	1 rw "BIOS owned semaphore";
128    };
129};
130
131    
132	    
133
134    
135    
136	
137