1/*
2 * Copyright (c) 2014 ETH Zurich.
3 * All rights reserved.
4 *
5 * This file is distributed under the terms in the attached LICENSE file.
6 * If you do not find this file, copies can be found by writing to:
7 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group.
8 */
9
10#ifndef XEON_PHI_H_
11#define XEON_PHI_H_
12
13#include <xeon_phi/xeon_phi.h>
14#include <collections/hash_table.h>
15
16#include "debug.h"
17
18/*
19 * Common setting values
20 */
21
22/// the name of the Xeon Phi bootloader image
23#define XEON_PHI_BOOTLOADER "/weever"
24
25/// name of the file containing the modules to be loaded
26#define XEON_PHI_MOD_LIST "menu.lst.k1om"
27
28/// the name fo the nfs path to mount
29#define XEON_PHI_NFS_PATH NULL
30
31/// path where the NFS directory will be mounted
32#define XEON_PHI_NFS_MNT "/xeon_phi"
33
34/// if we use MSIX interrupts or legacy interrupts
35#define XEON_PHI_MSIX_ENABLED 1
36
37/// the number of MSIX interrupts we use
38#define XEON_PHI_MSIX_NUM     1
39
40/// the initial aperture size mapped to boot the card
41#define XEON_PHI_APERTURE_INIT_SIZE (1024*1024*1024)
42
43
44#define XEON_PHI_IS_CLIENT 0x0
45#define XEON_PHI_IS_HOST   0x1
46
47/*
48 * This defines are used to reference the MMIO registers on the host side.
49 *
50 * The Mackerel Specifications use the SBOX or DBOX baseaddress as their
51 * register base. however the SBOX or DBOX have a certain offset into the
52 * MMIO range.
53 */
54#define XEON_PHI_HOST_DBOX_OFFSET      0x00000000
55#define XEON_PHI_HOST_SBOX_OFFSET      0x00010000
56
57#define XEON_PHI_MMIO_TO_SBOX(phi) \
58    ((void *)((lvaddr_t)(phi->mmio.vbase)+XEON_PHI_HOST_SBOX_OFFSET))
59#define XEON_PHI_MMIO_TO_DBOX(phi) \
60    ((void *)((lvaddr_t)(phi->mmio.vbase)+XEON_PHI_HOST_DBOX_OFFSET))
61
62/*
63 * --------------------------------------------------------------------------
64 * Xeon Phi Management structure
65 */
66
67/// represents the state of the Xeon Phi
68typedef enum xeon_phi_state
69{
70    XEON_PHI_STATE_NULL,    ///< The card has not yet been initialized
71    XEON_PHI_STATE_PCI_OK,  ///< The card has been registered with PCI
72    XEON_PHI_STATE_RESET,   ///< The card has been reset
73    XEON_PHI_STATE_READY,   ///< The card is ready to load the os
74    XEON_PHI_STATE_BOOTING,  ///< The card is in the booting state
75    XEON_PHI_STATE_ONLINE   ///< the card has booted and is online
76} xeon_phi_state_t;
77
78typedef enum xnode_state
79{
80    XNODE_STATE_NONE,
81    XNODE_STATE_REGISTERING,
82    XNODE_STATE_WAIT_CONNECTION,
83    XNODE_STATE_READY,
84    XNODE_STATE_FAILURE
85} xnode_state_t;
86
87/// represents the memory ranges occupied by the Xeon Phi card
88struct mbar
89{
90    lvaddr_t vbase;     ///< virtual address of the mbar if mapped
91    lpaddr_t pbase;     ///< physical address of the mbar
92    size_t length;      ///< length of the mapped area
93    struct capref cap;  ///< capability of the mbar
94    size_t  bytes;      ///< size of the region in bytes
95};
96
97struct xnode
98{
99    struct xeon_phi_driver_binding *binding;
100    iref_t iref;
101    xnode_state_t state;
102    uint8_t bootstrap_done;
103    errval_t err;
104    uint8_t id;
105    lpaddr_t apt_base;
106    size_t apt_size;
107    struct msg_info *msg;
108    struct xeon_phi *local;
109};
110
111struct xeon_phi
112{
113    xeon_phi_state_t state;
114    struct mbar mmio;       ///< pointer to the MMIO address range
115    struct mbar apt;        ///< pointer to the aperture address range
116
117    lvaddr_t os_offset;     ///< offset of the OS image into the aperture
118    uint32_t os_size;       ///< the size of the OS image
119    char *cmdline;          ///< pointer to the bootloader cmdline
120    uint32_t cmdlen;        ///< the length of the cmd line
121
122    uint8_t id;             ///< card id for identifying the card
123    iref_t iref;
124    uint32_t apicid;        ///< APIC id used for sending the boot interrupt
125
126    uint8_t connected;      ///< number of connected xphis
127    struct xnode topology[XEON_PHI_NUM_MAX];
128
129    domainid_t current_key;
130    collections_hash_table* did_to_cap; ///< hash table to translate caps to dids
131
132    uint8_t is_client;
133
134    iref_t xphi_svc_iref;
135
136    struct smpt_info *smpt;  ///< pointer to the SMPT information struct
137    struct irq_info *irq;   ///< pointer to the IRQ information struct
138    struct dma_device *dma;   ///< pointer to the DMA information struct
139    struct msg_info *msg;   ///< pointer to the Messaging information struct
140};
141
142/**
143 * \brief starts the serial receive thread
144 *
145 * \param phi   pointer to the card information
146 */
147errval_t xeon_phi_serial_start_recv_thread(struct xeon_phi *phi);
148
149/**
150 * \brief initializes the serial receiver
151 *
152 * \param phi   pointer to the card information
153 */
154errval_t xeon_phi_serial_init(struct xeon_phi *phi);
155
156/**
157 * \brief checks if there is a message waiting on the serial and reads
158 *        it into the buffer.
159 *
160 * \return 0: There was no message
161 *         1: There was a message waiting and it porocessed.
162 */
163uint32_t xeon_phi_serial_handle_recv(void);
164
165/**
166 * \brief boots the card with the given loader and multiboot image
167 *
168 * \param phi           pointer to the card information
169 * \param xloader_img   pointer to the card bootloader image
170 * \param multiboot_img pointer to the card multiboot image
171 */
172errval_t xeon_phi_boot(struct xeon_phi *phi,
173                       char *xloader_img,
174                       char *multiboot_img);
175
176/**
177 * \brief performs a soft reset of the card
178 *
179 * \param phi   pointer to the card information
180 */
181errval_t xeon_phi_reset(struct xeon_phi *phi);
182
183/**
184 * \brief initializes the coprocessor card
185 *
186 * \param phi pointer to the information structure
187 */
188errval_t xeon_phi_init(struct xeon_phi *phi,
189                       uint32_t bus,
190                       uint32_t dev,
191                       uint32_t fun);
192
193/**
194 * \brief maps the aperture memory range of the Xeon Phi into the drivers
195 *        vspace to be able to load the coprocessor OS onto the card
196 *
197 * \param phi   pointer to the Xeon Phi structure holding aperture information
198 * \param range how much bytes to map
199 *
200 * \returns SYS_ERR_OK on success
201 */
202errval_t xeon_phi_map_aperture(struct xeon_phi *phi,
203                               size_t range);
204
205/**
206 * \brief unmaps the previously mapped aperture range when the programming
207 *        completes.
208 *
209 * \param phi pointer to the Xeon Phi structure holiding mapping information
210 *
211 * \return SYS_ERR_OK on success
212 */
213errval_t xeon_phi_unmap_aperture(struct xeon_phi *phi);
214
215/**
216 * \brief handles events on the waitset and polls for completed DMA transfers
217 *        and new data on the serial line (host only)
218 *
219 * \param do_yield if set, yield thread if no event was discovered
220 *
221 * \return SYS_ERR_OK if an event was handled
222 *         LIB_ERR_NO_EVENT if there was no evetn
223 */
224errval_t xeon_phi_event_poll(uint8_t do_yield);
225
226
227#endif /* XEON_PHI_H_ */
228