1/*- 2 * Copyright 2006-2009 Solarflare Communications Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#ifndef _SYS_EFX_H 27#define _SYS_EFX_H 28 29#include "efsys.h" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1])) 36 37#define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0])) 38 39#ifndef EFSYS_MEM_IS_NULL 40#define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL) 41#endif 42 43typedef enum efx_family_e { 44 EFX_FAMILY_INVALID, 45 EFX_FAMILY_FALCON, 46 EFX_FAMILY_SIENA, 47 EFX_FAMILY_NTYPES 48} efx_family_t; 49 50extern __checkReturn int 51efx_family( 52 __in uint16_t venid, 53 __in uint16_t devid, 54 __out efx_family_t *efp); 55 56extern __checkReturn int 57efx_infer_family( 58 __in efsys_bar_t *esbp, 59 __out efx_family_t *efp); 60 61#define EFX_PCI_VENID_SFC 0x1924 62#define EFX_PCI_DEVID_FALCON 0x0710 63#define EFX_PCI_DEVID_BETHPAGE 0x0803 64#define EFX_PCI_DEVID_SIENA 0x0813 65#define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 66 67#define EFX_MEM_BAR 2 68 69/* Error codes */ 70 71enum { 72 EFX_ERR_INVALID, 73 EFX_ERR_SRAM_OOB, 74 EFX_ERR_BUFID_DC_OOB, 75 EFX_ERR_MEM_PERR, 76 EFX_ERR_RBUF_OWN, 77 EFX_ERR_TBUF_OWN, 78 EFX_ERR_RDESQ_OWN, 79 EFX_ERR_TDESQ_OWN, 80 EFX_ERR_EVQ_OWN, 81 EFX_ERR_EVFF_OFLO, 82 EFX_ERR_ILL_ADDR, 83 EFX_ERR_SRAM_PERR, 84 EFX_ERR_NCODES 85}; 86 87/* NIC */ 88 89typedef struct efx_nic_s efx_nic_t; 90 91extern __checkReturn int 92efx_nic_create( 93 __in efx_family_t family, 94 __in efsys_identifier_t *esip, 95 __in efsys_bar_t *esbp, 96 __in efsys_lock_t *eslp, 97 __deref_out efx_nic_t **enpp); 98 99extern __checkReturn int 100efx_nic_probe( 101 __in efx_nic_t *enp); 102 103#if EFSYS_OPT_PCIE_TUNE 104 105extern __checkReturn int 106efx_nic_pcie_tune( 107 __in efx_nic_t *enp, 108 unsigned int nlanes); 109 110extern __checkReturn int 111efx_nic_pcie_extended_sync( 112 __in efx_nic_t *enp); 113 114#endif /* EFSYS_OPT_PCIE_TUNE */ 115 116extern __checkReturn int 117efx_nic_init( 118 __in efx_nic_t *enp); 119 120extern __checkReturn int 121efx_nic_reset( 122 __in efx_nic_t *enp); 123 124#if EFSYS_OPT_DIAG 125 126extern __checkReturn int 127efx_nic_register_test( 128 __in efx_nic_t *enp); 129 130#endif /* EFSYS_OPT_DIAG */ 131 132extern void 133efx_nic_fini( 134 __in efx_nic_t *enp); 135 136extern void 137efx_nic_unprobe( 138 __in efx_nic_t *enp); 139 140extern void 141efx_nic_destroy( 142 __in efx_nic_t *enp); 143 144#if EFSYS_OPT_MCDI 145 146typedef struct efx_mcdi_req_s efx_mcdi_req_t; 147 148typedef enum efx_mcdi_exception_e { 149 EFX_MCDI_EXCEPTION_MC_REBOOT, 150 EFX_MCDI_EXCEPTION_MC_BADASSERT, 151} efx_mcdi_exception_t; 152 153typedef struct efx_mcdi_transport_s { 154 void *emt_context; 155 void (*emt_execute)(void *, efx_mcdi_req_t *); 156 void (*emt_ev_cpl)(void *); 157 void (*emt_exception)(void *, efx_mcdi_exception_t); 158} efx_mcdi_transport_t; 159 160extern __checkReturn int 161efx_mcdi_init( 162 __in efx_nic_t *enp, 163 __in const efx_mcdi_transport_t *mtp); 164 165extern __checkReturn int 166efx_mcdi_reboot( 167 __in efx_nic_t *enp); 168 169extern void 170efx_mcdi_request_start( 171 __in efx_nic_t *enp, 172 __in efx_mcdi_req_t *emrp, 173 __in boolean_t ev_cpl); 174 175extern __checkReturn boolean_t 176efx_mcdi_request_poll( 177 __in efx_nic_t *enp); 178 179extern __checkReturn boolean_t 180efx_mcdi_request_abort( 181 __in efx_nic_t *enp); 182 183extern void 184efx_mcdi_fini( 185 __in efx_nic_t *enp); 186 187#endif /* EFSYS_OPT_MCDI */ 188 189/* INTR */ 190 191#define EFX_NINTR_FALCON 64 192#define EFX_NINTR_SIENA 1024 193 194typedef enum efx_intr_type_e { 195 EFX_INTR_INVALID = 0, 196 EFX_INTR_LINE, 197 EFX_INTR_MESSAGE, 198 EFX_INTR_NTYPES 199} efx_intr_type_t; 200 201#define EFX_INTR_SIZE (sizeof (efx_oword_t)) 202 203extern __checkReturn int 204efx_intr_init( 205 __in efx_nic_t *enp, 206 __in efx_intr_type_t type, 207 __in efsys_mem_t *esmp); 208 209extern void 210efx_intr_enable( 211 __in efx_nic_t *enp); 212 213extern void 214efx_intr_disable( 215 __in efx_nic_t *enp); 216 217extern void 218efx_intr_disable_unlocked( 219 __in efx_nic_t *enp); 220 221#define EFX_INTR_NEVQS 32 222 223extern __checkReturn int 224efx_intr_trigger( 225 __in efx_nic_t *enp, 226 __in unsigned int level); 227 228extern void 229efx_intr_status_line( 230 __in efx_nic_t *enp, 231 __out boolean_t *fatalp, 232 __out uint32_t *maskp); 233 234extern void 235efx_intr_status_message( 236 __in efx_nic_t *enp, 237 __in unsigned int message, 238 __out boolean_t *fatalp); 239 240extern void 241efx_intr_fatal( 242 __in efx_nic_t *enp); 243 244extern void 245efx_intr_fini( 246 __in efx_nic_t *enp); 247 248/* MAC */ 249 250#if EFSYS_OPT_MAC_STATS 251 252/* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */ 253typedef enum efx_mac_stat_e { 254 EFX_MAC_RX_OCTETS, 255 EFX_MAC_RX_PKTS, 256 EFX_MAC_RX_UNICST_PKTS, 257 EFX_MAC_RX_MULTICST_PKTS, 258 EFX_MAC_RX_BRDCST_PKTS, 259 EFX_MAC_RX_PAUSE_PKTS, 260 EFX_MAC_RX_LE_64_PKTS, 261 EFX_MAC_RX_65_TO_127_PKTS, 262 EFX_MAC_RX_128_TO_255_PKTS, 263 EFX_MAC_RX_256_TO_511_PKTS, 264 EFX_MAC_RX_512_TO_1023_PKTS, 265 EFX_MAC_RX_1024_TO_15XX_PKTS, 266 EFX_MAC_RX_GE_15XX_PKTS, 267 EFX_MAC_RX_ERRORS, 268 EFX_MAC_RX_FCS_ERRORS, 269 EFX_MAC_RX_DROP_EVENTS, 270 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 271 EFX_MAC_RX_SYMBOL_ERRORS, 272 EFX_MAC_RX_ALIGN_ERRORS, 273 EFX_MAC_RX_INTERNAL_ERRORS, 274 EFX_MAC_RX_JABBER_PKTS, 275 EFX_MAC_RX_LANE0_CHAR_ERR, 276 EFX_MAC_RX_LANE1_CHAR_ERR, 277 EFX_MAC_RX_LANE2_CHAR_ERR, 278 EFX_MAC_RX_LANE3_CHAR_ERR, 279 EFX_MAC_RX_LANE0_DISP_ERR, 280 EFX_MAC_RX_LANE1_DISP_ERR, 281 EFX_MAC_RX_LANE2_DISP_ERR, 282 EFX_MAC_RX_LANE3_DISP_ERR, 283 EFX_MAC_RX_MATCH_FAULT, 284 EFX_MAC_RX_NODESC_DROP_CNT, 285 EFX_MAC_TX_OCTETS, 286 EFX_MAC_TX_PKTS, 287 EFX_MAC_TX_UNICST_PKTS, 288 EFX_MAC_TX_MULTICST_PKTS, 289 EFX_MAC_TX_BRDCST_PKTS, 290 EFX_MAC_TX_PAUSE_PKTS, 291 EFX_MAC_TX_LE_64_PKTS, 292 EFX_MAC_TX_65_TO_127_PKTS, 293 EFX_MAC_TX_128_TO_255_PKTS, 294 EFX_MAC_TX_256_TO_511_PKTS, 295 EFX_MAC_TX_512_TO_1023_PKTS, 296 EFX_MAC_TX_1024_TO_15XX_PKTS, 297 EFX_MAC_TX_GE_15XX_PKTS, 298 EFX_MAC_TX_ERRORS, 299 EFX_MAC_TX_SGL_COL_PKTS, 300 EFX_MAC_TX_MULT_COL_PKTS, 301 EFX_MAC_TX_EX_COL_PKTS, 302 EFX_MAC_TX_LATE_COL_PKTS, 303 EFX_MAC_TX_DEF_PKTS, 304 EFX_MAC_TX_EX_DEF_PKTS, 305 EFX_MAC_NSTATS 306} efx_mac_stat_t; 307 308/* END MKCONFIG GENERATED EfxHeaderMacBlock */ 309 310#endif /* EFSYS_OPT_MAC_STATS */ 311 312typedef enum efx_link_mode_e { 313 EFX_LINK_UNKNOWN = 0, 314 EFX_LINK_DOWN, 315 EFX_LINK_10HDX, 316 EFX_LINK_10FDX, 317 EFX_LINK_100HDX, 318 EFX_LINK_100FDX, 319 EFX_LINK_1000HDX, 320 EFX_LINK_1000FDX, 321 EFX_LINK_10000FDX, 322 EFX_LINK_NMODES 323} efx_link_mode_t; 324 325#define EFX_MAC_SDU_MAX 9202 326 327#define EFX_MAC_PDU(_sdu) \ 328 P2ROUNDUP(((_sdu) \ 329 + /* EtherII */ 14 \ 330 + /* VLAN */ 4 \ 331 + /* CRC */ 4 \ 332 + /* bug16011 */ 16), \ 333 (1 << 3)) 334 335#define EFX_MAC_PDU_MIN 60 336#define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 337 338extern __checkReturn int 339efx_mac_pdu_set( 340 __in efx_nic_t *enp, 341 __in size_t pdu); 342 343extern __checkReturn int 344efx_mac_addr_set( 345 __in efx_nic_t *enp, 346 __in uint8_t *addr); 347 348extern __checkReturn int 349efx_mac_filter_set( 350 __in efx_nic_t *enp, 351 __in boolean_t unicst, 352 __in boolean_t brdcst); 353 354extern __checkReturn int 355efx_mac_drain( 356 __in efx_nic_t *enp, 357 __in boolean_t enabled); 358 359extern __checkReturn int 360efx_mac_up( 361 __in efx_nic_t *enp, 362 __out boolean_t *mac_upp); 363 364#define EFX_FCNTL_RESPOND 0x00000001 365#define EFX_FCNTL_GENERATE 0x00000002 366 367extern __checkReturn int 368efx_mac_fcntl_set( 369 __in efx_nic_t *enp, 370 __in unsigned int fcntl, 371 __in boolean_t autoneg); 372 373extern void 374efx_mac_fcntl_get( 375 __in efx_nic_t *enp, 376 __out unsigned int *fcntl_wantedp, 377 __out unsigned int *fcntl_linkp); 378 379#define EFX_MAC_HASH_BITS (1 << 8) 380 381extern __checkReturn int 382efx_mac_hash_set( 383 __in efx_nic_t *enp, 384 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); 385 386#if EFSYS_OPT_MAC_STATS 387 388#if EFSYS_OPT_NAMES 389 390extern __checkReturn const char __cs * 391efx_mac_stat_name( 392 __in efx_nic_t *enp, 393 __in unsigned int id); 394 395#endif /* EFSYS_OPT_NAMES */ 396 397#define EFX_MAC_STATS_SIZE 0x400 398 399/* 400 * Upload mac statistics supported by the hardware into the given buffer. 401 * 402 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes, 403 * and page aligned. 404 * 405 * The hardware will only DMA statistics that it understands (of course). 406 * Drivers should not make any assumptions about which statistics are 407 * supported, especially when the statistics are generated by firmware. 408 * 409 * Thus, drivers should zero this buffer before use, so that not-understood 410 * statistics read back as zero. 411 */ 412extern __checkReturn int 413efx_mac_stats_upload( 414 __in efx_nic_t *enp, 415 __in efsys_mem_t *esmp); 416 417extern __checkReturn int 418efx_mac_stats_periodic( 419 __in efx_nic_t *enp, 420 __in efsys_mem_t *esmp, 421 __in uint16_t period_ms, 422 __in boolean_t events); 423 424extern __checkReturn int 425efx_mac_stats_update( 426 __in efx_nic_t *enp, 427 __in efsys_mem_t *esmp, 428 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 429 __out_opt uint32_t *generationp); 430 431#endif /* EFSYS_OPT_MAC_STATS */ 432 433/* MON */ 434 435typedef enum efx_mon_type_e { 436 EFX_MON_INVALID = 0, 437 EFX_MON_NULL, 438 EFX_MON_LM87, 439 EFX_MON_MAX6647, 440 EFX_MON_SFC90X0, 441 EFX_MON_NTYPES 442} efx_mon_type_t; 443 444#if EFSYS_OPT_NAMES 445 446extern const char __cs * 447efx_mon_name( 448 __in efx_nic_t *enp); 449 450#endif /* EFSYS_OPT_NAMES */ 451 452extern __checkReturn int 453efx_mon_init( 454 __in efx_nic_t *enp); 455 456#if EFSYS_OPT_MON_STATS 457 458#define EFX_MON_STATS_SIZE 0x100 459 460/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 16a14e61aa4f8d80 */ 461typedef enum efx_mon_stat_e { 462 EFX_MON_STAT_2_5V, 463 EFX_MON_STAT_VCCP1, 464 EFX_MON_STAT_VCC, 465 EFX_MON_STAT_5V, 466 EFX_MON_STAT_12V, 467 EFX_MON_STAT_VCCP2, 468 EFX_MON_STAT_EXT_TEMP, 469 EFX_MON_STAT_INT_TEMP, 470 EFX_MON_STAT_AIN1, 471 EFX_MON_STAT_AIN2, 472 EFX_MON_STAT_INT_COOLING, 473 EFX_MON_STAT_EXT_COOLING, 474 EFX_MON_STAT_1V, 475 EFX_MON_STAT_1_2V, 476 EFX_MON_STAT_1_8V, 477 EFX_MON_STAT_3_3V, 478 EFX_MON_NSTATS 479} efx_mon_stat_t; 480 481/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 482 483typedef enum efx_mon_stat_state_e { 484 EFX_MON_STAT_STATE_OK = 0, 485 EFX_MON_STAT_STATE_WARNING = 1, 486 EFX_MON_STAT_STATE_FATAL = 2, 487 EFX_MON_STAT_STATE_BROKEN = 3, 488} efx_mon_stat_state_t; 489 490typedef struct efx_mon_stat_value_t { 491 uint16_t emsv_value; 492 uint16_t emsv_state; 493} efx_mon_stat_value_t; 494 495#if EFSYS_OPT_NAMES 496 497extern const char __cs * 498efx_mon_stat_name( 499 __in efx_nic_t *enp, 500 __in efx_mon_stat_t id); 501 502#endif /* EFSYS_OPT_NAMES */ 503 504extern __checkReturn int 505efx_mon_stats_update( 506 __in efx_nic_t *enp, 507 __in efsys_mem_t *esmp, 508 __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 509 510#endif /* EFSYS_OPT_MON_STATS */ 511 512extern void 513efx_mon_fini( 514 __in efx_nic_t *enp); 515 516/* PHY */ 517 518#define PMA_PMD_MMD 1 519#define PCS_MMD 3 520#define PHY_XS_MMD 4 521#define DTE_XS_MMD 5 522#define AN_MMD 7 523#define CL22EXT_MMD 29 524 525#define MAXMMD ((1 << 5) - 1) 526 527/* PHY types */ 528#define EFX_PHY_NULL 0x0 529#define EFX_PHY_TXC43128 0x1 530#define EFX_PHY_SFX7101 0x3 531#define EFX_PHY_QT2022C2 0x4 532#define EFX_PHY_SFT9001A 0x8 533#define EFX_PHY_QT2025C 0x9 534#define EFX_PHY_SFT9001B 0xa 535#define EFX_PHY_QLX111V 0xc 536 537extern __checkReturn int 538efx_phy_verify( 539 __in efx_nic_t *enp); 540 541#if EFSYS_OPT_PHY_LED_CONTROL 542 543typedef enum efx_phy_led_mode_e { 544 EFX_PHY_LED_DEFAULT = 0, 545 EFX_PHY_LED_OFF, 546 EFX_PHY_LED_ON, 547 EFX_PHY_LED_FLASH, 548 EFX_PHY_LED_NMODES 549} efx_phy_led_mode_t; 550 551extern __checkReturn int 552efx_phy_led_set( 553 __in efx_nic_t *enp, 554 __in efx_phy_led_mode_t mode); 555 556#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 557 558extern __checkReturn int 559efx_port_init( 560 __in efx_nic_t *enp); 561 562#if EFSYS_OPT_LOOPBACK 563 564typedef enum efx_loopback_type_e { 565 EFX_LOOPBACK_OFF = 0, 566 EFX_LOOPBACK_DATA = 1, 567 EFX_LOOPBACK_GMAC = 2, 568 EFX_LOOPBACK_XGMII = 3, 569 EFX_LOOPBACK_XGXS = 4, 570 EFX_LOOPBACK_XAUI = 5, 571 EFX_LOOPBACK_GMII = 6, 572 EFX_LOOPBACK_SGMII = 7, 573 EFX_LOOPBACK_XGBR = 8, 574 EFX_LOOPBACK_XFI = 9, 575 EFX_LOOPBACK_XAUI_FAR = 10, 576 EFX_LOOPBACK_GMII_FAR = 11, 577 EFX_LOOPBACK_SGMII_FAR = 12, 578 EFX_LOOPBACK_XFI_FAR = 13, 579 EFX_LOOPBACK_GPHY = 14, 580 EFX_LOOPBACK_PHY_XS = 15, 581 EFX_LOOPBACK_PCS = 16, 582 EFX_LOOPBACK_PMA_PMD = 17, 583 EFX_LOOPBACK_NTYPES 584} efx_loopback_type_t; 585 586#define EFX_LOOPBACK_MAC_MASK \ 587 ((1 << EFX_LOOPBACK_DATA) | \ 588 (1 << EFX_LOOPBACK_GMAC) | \ 589 (1 << EFX_LOOPBACK_XGMII) | \ 590 (1 << EFX_LOOPBACK_XGXS) | \ 591 (1 << EFX_LOOPBACK_XAUI) | \ 592 (1 << EFX_LOOPBACK_GMII) | \ 593 (1 << EFX_LOOPBACK_SGMII) | \ 594 (1 << EFX_LOOPBACK_XGBR) | \ 595 (1 << EFX_LOOPBACK_XFI) | \ 596 (1 << EFX_LOOPBACK_XAUI_FAR) | \ 597 (1 << EFX_LOOPBACK_GMII_FAR) | \ 598 (1 << EFX_LOOPBACK_SGMII_FAR) | \ 599 (1 << EFX_LOOPBACK_XFI_FAR)) 600 601#define EFX_LOOPBACK_MASK \ 602 ((1 << EFX_LOOPBACK_NTYPES) - 1) 603 604extern __checkReturn int 605efx_port_loopback_set( 606 __in efx_nic_t *enp, 607 __in efx_link_mode_t link_mode, 608 __in efx_loopback_type_t type); 609 610#if EFSYS_OPT_NAMES 611 612extern __checkReturn const char __cs * 613efx_loopback_type_name( 614 __in efx_nic_t *enp, 615 __in efx_loopback_type_t type); 616 617#endif /* EFSYS_OPT_NAMES */ 618 619#endif /* EFSYS_OPT_LOOPBACK */ 620 621extern __checkReturn int 622efx_port_poll( 623 __in efx_nic_t *enp, 624 __out efx_link_mode_t *link_modep); 625 626extern void 627efx_port_fini( 628 __in efx_nic_t *enp); 629 630typedef enum efx_phy_cap_type_e { 631 EFX_PHY_CAP_INVALID = 0, 632 EFX_PHY_CAP_10HDX, 633 EFX_PHY_CAP_10FDX, 634 EFX_PHY_CAP_100HDX, 635 EFX_PHY_CAP_100FDX, 636 EFX_PHY_CAP_1000HDX, 637 EFX_PHY_CAP_1000FDX, 638 EFX_PHY_CAP_10000FDX, 639 EFX_PHY_CAP_PAUSE, 640 EFX_PHY_CAP_ASYM, 641 EFX_PHY_CAP_AN, 642 EFX_PHY_CAP_NTYPES 643} efx_phy_cap_type_t; 644 645 646#define EFX_PHY_CAP_CURRENT 0x00000000 647#define EFX_PHY_CAP_DEFAULT 0x00000001 648#define EFX_PHY_CAP_PERM 0x00000002 649 650extern void 651efx_phy_adv_cap_get( 652 __in efx_nic_t *enp, 653 __in uint32_t flag, 654 __out uint32_t *maskp); 655 656extern __checkReturn int 657efx_phy_adv_cap_set( 658 __in efx_nic_t *enp, 659 __in uint32_t mask); 660 661extern void 662efx_phy_lp_cap_get( 663 __in efx_nic_t *enp, 664 __out uint32_t *maskp); 665 666extern __checkReturn int 667efx_phy_oui_get( 668 __in efx_nic_t *enp, 669 __out uint32_t *ouip); 670 671typedef enum efx_phy_media_type_e { 672 EFX_PHY_MEDIA_INVALID = 0, 673 EFX_PHY_MEDIA_XAUI, 674 EFX_PHY_MEDIA_CX4, 675 EFX_PHY_MEDIA_KX4, 676 EFX_PHY_MEDIA_XFP, 677 EFX_PHY_MEDIA_SFP_PLUS, 678 EFX_PHY_MEDIA_BASE_T, 679 EFX_PHY_MEDIA_NTYPES 680} efx_phy_media_type_t; 681 682/* Get the type of medium currently used. If the board has ports for 683 * modules, a module is present, and we recognise the media type of 684 * the module, then this will be the media type of the module. 685 * Otherwise it will be the media type of the port. 686 */ 687extern void 688efx_phy_media_type_get( 689 __in efx_nic_t *enp, 690 __out efx_phy_media_type_t *typep); 691 692#if EFSYS_OPT_PHY_STATS 693 694/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 695typedef enum efx_phy_stat_e { 696 EFX_PHY_STAT_OUI, 697 EFX_PHY_STAT_PMA_PMD_LINK_UP, 698 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 699 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 700 EFX_PHY_STAT_PMA_PMD_REV_A, 701 EFX_PHY_STAT_PMA_PMD_REV_B, 702 EFX_PHY_STAT_PMA_PMD_REV_C, 703 EFX_PHY_STAT_PMA_PMD_REV_D, 704 EFX_PHY_STAT_PCS_LINK_UP, 705 EFX_PHY_STAT_PCS_RX_FAULT, 706 EFX_PHY_STAT_PCS_TX_FAULT, 707 EFX_PHY_STAT_PCS_BER, 708 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 709 EFX_PHY_STAT_PHY_XS_LINK_UP, 710 EFX_PHY_STAT_PHY_XS_RX_FAULT, 711 EFX_PHY_STAT_PHY_XS_TX_FAULT, 712 EFX_PHY_STAT_PHY_XS_ALIGN, 713 EFX_PHY_STAT_PHY_XS_SYNC_A, 714 EFX_PHY_STAT_PHY_XS_SYNC_B, 715 EFX_PHY_STAT_PHY_XS_SYNC_C, 716 EFX_PHY_STAT_PHY_XS_SYNC_D, 717 EFX_PHY_STAT_AN_LINK_UP, 718 EFX_PHY_STAT_AN_MASTER, 719 EFX_PHY_STAT_AN_LOCAL_RX_OK, 720 EFX_PHY_STAT_AN_REMOTE_RX_OK, 721 EFX_PHY_STAT_CL22EXT_LINK_UP, 722 EFX_PHY_STAT_SNR_A, 723 EFX_PHY_STAT_SNR_B, 724 EFX_PHY_STAT_SNR_C, 725 EFX_PHY_STAT_SNR_D, 726 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 727 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 728 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 729 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 730 EFX_PHY_STAT_AN_COMPLETE, 731 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 732 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 733 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 734 EFX_PHY_STAT_PCS_FW_VERSION_0, 735 EFX_PHY_STAT_PCS_FW_VERSION_1, 736 EFX_PHY_STAT_PCS_FW_VERSION_2, 737 EFX_PHY_STAT_PCS_FW_VERSION_3, 738 EFX_PHY_STAT_PCS_FW_BUILD_YY, 739 EFX_PHY_STAT_PCS_FW_BUILD_MM, 740 EFX_PHY_STAT_PCS_FW_BUILD_DD, 741 EFX_PHY_STAT_PCS_OP_MODE, 742 EFX_PHY_NSTATS 743} efx_phy_stat_t; 744 745/* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 746 747#if EFSYS_OPT_NAMES 748 749extern const char __cs * 750efx_phy_stat_name( 751 __in efx_nic_t *enp, 752 __in efx_phy_stat_t stat); 753 754#endif /* EFSYS_OPT_NAMES */ 755 756#define EFX_PHY_STATS_SIZE 0x100 757 758extern __checkReturn int 759efx_phy_stats_update( 760 __in efx_nic_t *enp, 761 __in efsys_mem_t *esmp, 762 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); 763 764#endif /* EFSYS_OPT_PHY_STATS */ 765 766#if EFSYS_OPT_PHY_PROPS 767 768#if EFSYS_OPT_NAMES 769 770extern const char __cs * 771efx_phy_prop_name( 772 __in efx_nic_t *enp, 773 __in unsigned int id); 774 775#endif /* EFSYS_OPT_NAMES */ 776 777#define EFX_PHY_PROP_DEFAULT 0x00000001 778 779extern __checkReturn int 780efx_phy_prop_get( 781 __in efx_nic_t *enp, 782 __in unsigned int id, 783 __in uint32_t flags, 784 __out uint32_t *valp); 785 786extern __checkReturn int 787efx_phy_prop_set( 788 __in efx_nic_t *enp, 789 __in unsigned int id, 790 __in uint32_t val); 791 792#endif /* EFSYS_OPT_PHY_PROPS */ 793 794#if EFSYS_OPT_PHY_BIST 795 796typedef enum efx_phy_bist_type_e { 797 EFX_PHY_BIST_TYPE_UNKNOWN, 798 EFX_PHY_BIST_TYPE_NORMAL, 799 EFX_PHY_BIST_TYPE_CABLE_SHORT, 800 EFX_PHY_BIST_TYPE_CABLE_LONG, 801 EFX_PHY_BIST_TYPE_NTYPES, 802} efx_phy_bist_type_t; 803 804typedef enum efx_phy_bist_result_e { 805 EFX_PHY_BIST_RESULT_UNKNOWN, 806 EFX_PHY_BIST_RESULT_RUNNING, 807 EFX_PHY_BIST_RESULT_PASSED, 808 EFX_PHY_BIST_RESULT_FAILED, 809} efx_phy_bist_result_t; 810 811typedef enum efx_phy_cable_status_e { 812 EFX_PHY_CABLE_STATUS_OK, 813 EFX_PHY_CABLE_STATUS_INVALID, 814 EFX_PHY_CABLE_STATUS_OPEN, 815 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 816 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 817 EFX_PHY_CABLE_STATUS_BUSY, 818} efx_phy_cable_status_t; 819 820typedef enum efx_phy_bist_value_e { 821 EFX_PHY_BIST_CABLE_LENGTH_A, 822 EFX_PHY_BIST_CABLE_LENGTH_B, 823 EFX_PHY_BIST_CABLE_LENGTH_C, 824 EFX_PHY_BIST_CABLE_LENGTH_D, 825 EFX_PHY_BIST_CABLE_STATUS_A, 826 EFX_PHY_BIST_CABLE_STATUS_B, 827 EFX_PHY_BIST_CABLE_STATUS_C, 828 EFX_PHY_BIST_CABLE_STATUS_D, 829 EFX_PHY_BIST_FAULT_CODE, 830 EFX_PHY_BIST_NVALUES, 831} efx_phy_bist_value_t; 832 833extern __checkReturn int 834efx_phy_bist_start( 835 __in efx_nic_t *enp, 836 __in efx_phy_bist_type_t type); 837 838extern __checkReturn int 839efx_phy_bist_poll( 840 __in efx_nic_t *enp, 841 __in efx_phy_bist_type_t type, 842 __out efx_phy_bist_result_t *resultp, 843 __out_opt uint32_t *value_maskp, 844 __out_ecount_opt(count) unsigned long *valuesp, 845 __in size_t count); 846 847extern void 848efx_phy_bist_stop( 849 __in efx_nic_t *enp, 850 __in efx_phy_bist_type_t type); 851 852#endif /* EFSYS_OPT_PHY_BIST */ 853 854#define EFX_FEATURE_IPV6 0x00000001 855#define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 856#define EFX_FEATURE_LINK_EVENTS 0x00000004 857#define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 858#define EFX_FEATURE_WOL 0x00000010 859#define EFX_FEATURE_MCDI 0x00000020 860#define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 861#define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 862 863typedef struct efx_nic_cfg_s { 864 uint32_t enc_board_type; 865 uint32_t enc_phy_type; 866#if EFSYS_OPT_NAMES 867 char enc_phy_name[21]; 868#endif 869 char enc_phy_revision[21]; 870 efx_mon_type_t enc_mon_type; 871#if EFSYS_OPT_MON_STATS 872 uint32_t enc_mon_stat_mask; 873#endif 874 unsigned int enc_features; 875 uint8_t enc_mac_addr[6]; 876 uint8_t enc_port; 877 uint32_t enc_evq_limit; 878 uint32_t enc_txq_limit; 879 uint32_t enc_rxq_limit; 880 uint32_t enc_buftbl_limit; 881 uint32_t enc_evq_moderation_max; 882#if EFSYS_OPT_LOOPBACK 883 uint32_t enc_loopback_types[EFX_LINK_NMODES]; 884#endif /* EFSYS_OPT_LOOPBACK */ 885#if EFSYS_OPT_PHY_FLAGS 886 uint32_t enc_phy_flags_mask; 887#endif /* EFSYS_OPT_PHY_FLAGS */ 888#if EFSYS_OPT_PHY_LED_CONTROL 889 uint32_t enc_led_mask; 890#endif /* EFSYS_OPT_PHY_LED_CONTROL */ 891#if EFSYS_OPT_PHY_STATS 892 uint64_t enc_phy_stat_mask; 893#endif /* EFSYS_OPT_PHY_STATS */ 894#if EFSYS_OPT_PHY_PROPS 895 unsigned int enc_phy_nprops; 896#endif /* EFSYS_OPT_PHY_PROPS */ 897#if EFSYS_OPT_SIENA 898 uint8_t enc_siena_channel; 899#if EFSYS_OPT_PHY_STATS 900 uint32_t enc_siena_phy_stat_mask; 901#endif /* EFSYS_OPT_PHY_STATS */ 902#if EFSYS_OPT_MON_STATS 903 uint32_t enc_siena_mon_stat_mask; 904#endif /* EFSYS_OPT_MON_STATS */ 905#endif /* EFSYS_OPT_SIENA */ 906#if EFSYS_OPT_PHY_BIST 907 uint32_t enc_bist_mask; 908#endif /* EFSYS_OPT_PHY_BIST */ 909} efx_nic_cfg_t; 910 911extern const efx_nic_cfg_t * 912efx_nic_cfg_get( 913 __in efx_nic_t *enp); 914 915#if EFSYS_OPT_VPD 916 917typedef enum efx_vpd_tag_e { 918 EFX_VPD_ID = 0x02, 919 EFX_VPD_END = 0x0f, 920 EFX_VPD_RO = 0x10, 921 EFX_VPD_RW = 0x11, 922} efx_vpd_tag_t; 923 924typedef uint16_t efx_vpd_keyword_t; 925 926typedef struct efx_vpd_value_s { 927 efx_vpd_tag_t evv_tag; 928 efx_vpd_keyword_t evv_keyword; 929 uint8_t evv_length; 930 uint8_t evv_value[0x100]; 931} efx_vpd_value_t; 932 933 934#define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 935 936extern __checkReturn int 937efx_vpd_init( 938 __in efx_nic_t *enp); 939 940extern __checkReturn int 941efx_vpd_size( 942 __in efx_nic_t *enp, 943 __out size_t *sizep); 944 945extern __checkReturn int 946efx_vpd_read( 947 __in efx_nic_t *enp, 948 __out_bcount(size) caddr_t data, 949 __in size_t size); 950 951extern __checkReturn int 952efx_vpd_verify( 953 __in efx_nic_t *enp, 954 __in_bcount(size) caddr_t data, 955 __in size_t size); 956 957extern __checkReturn int 958efx_vpd_reinit( 959 __in efx_nic_t *enp, 960 __in_bcount(size) caddr_t data, 961 __in size_t size); 962 963extern __checkReturn int 964efx_vpd_get( 965 __in efx_nic_t *enp, 966 __in_bcount(size) caddr_t data, 967 __in size_t size, 968 __inout efx_vpd_value_t *evvp); 969 970extern __checkReturn int 971efx_vpd_set( 972 __in efx_nic_t *enp, 973 __inout_bcount(size) caddr_t data, 974 __in size_t size, 975 __in efx_vpd_value_t *evvp); 976 977extern __checkReturn int 978efx_vpd_next( 979 __in efx_nic_t *enp, 980 __inout_bcount(size) caddr_t data, 981 __in size_t size, 982 __out efx_vpd_value_t *evvp, 983 __inout unsigned int *contp); 984 985extern __checkReturn int 986efx_vpd_write( 987 __in efx_nic_t *enp, 988 __in_bcount(size) caddr_t data, 989 __in size_t size); 990 991extern void 992efx_vpd_fini( 993 __in efx_nic_t *enp); 994 995#endif /* EFSYS_OPT_VPD */ 996 997/* NVRAM */ 998 999#if EFSYS_OPT_NVRAM 1000 1001typedef enum efx_nvram_type_e { 1002 EFX_NVRAM_INVALID = 0, 1003 EFX_NVRAM_BOOTROM, 1004 EFX_NVRAM_BOOTROM_CFG, 1005 EFX_NVRAM_MC_FIRMWARE, 1006 EFX_NVRAM_MC_GOLDEN, 1007 EFX_NVRAM_PHY, 1008 EFX_NVRAM_NULLPHY, 1009 EFX_NVRAM_NTYPES, 1010} efx_nvram_type_t; 1011 1012extern __checkReturn int 1013efx_nvram_init( 1014 __in efx_nic_t *enp); 1015 1016#if EFSYS_OPT_DIAG 1017 1018extern __checkReturn int 1019efx_nvram_test( 1020 __in efx_nic_t *enp); 1021 1022#endif /* EFSYS_OPT_DIAG */ 1023 1024extern __checkReturn int 1025efx_nvram_size( 1026 __in efx_nic_t *enp, 1027 __in efx_nvram_type_t type, 1028 __out size_t *sizep); 1029 1030extern __checkReturn int 1031efx_nvram_rw_start( 1032 __in efx_nic_t *enp, 1033 __in efx_nvram_type_t type, 1034 __out_opt size_t *pref_chunkp); 1035 1036extern void 1037efx_nvram_rw_finish( 1038 __in efx_nic_t *enp, 1039 __in efx_nvram_type_t type); 1040 1041extern __checkReturn int 1042efx_nvram_get_version( 1043 __in efx_nic_t *enp, 1044 __in efx_nvram_type_t type, 1045 __out uint32_t *subtypep, 1046 __out_ecount(4) uint16_t version[4]); 1047 1048extern __checkReturn int 1049efx_nvram_read_chunk( 1050 __in efx_nic_t *enp, 1051 __in efx_nvram_type_t type, 1052 __in unsigned int offset, 1053 __out_bcount(size) caddr_t data, 1054 __in size_t size); 1055 1056extern __checkReturn int 1057efx_nvram_set_version( 1058 __in efx_nic_t *enp, 1059 __in efx_nvram_type_t type, 1060 __out uint16_t version[4]); 1061 1062extern __checkReturn int 1063efx_nvram_erase( 1064 __in efx_nic_t *enp, 1065 __in efx_nvram_type_t type); 1066 1067extern __checkReturn int 1068efx_nvram_write_chunk( 1069 __in efx_nic_t *enp, 1070 __in efx_nvram_type_t type, 1071 __in unsigned int offset, 1072 __in_bcount(size) caddr_t data, 1073 __in size_t size); 1074 1075extern void 1076efx_nvram_fini( 1077 __in efx_nic_t *enp); 1078 1079#endif /* EFSYS_OPT_NVRAM */ 1080 1081#if EFSYS_OPT_BOOTCFG 1082 1083extern int 1084efx_bootcfg_read( 1085 __in efx_nic_t *enp, 1086 __out_bcount(size) caddr_t data, 1087 __in size_t size); 1088 1089extern int 1090efx_bootcfg_write( 1091 __in efx_nic_t *enp, 1092 __in_bcount(size) caddr_t data, 1093 __in size_t size); 1094 1095#endif /* EFSYS_OPT_BOOTCFG */ 1096 1097#if EFSYS_OPT_WOL 1098 1099typedef enum efx_wol_type_e { 1100 EFX_WOL_TYPE_INVALID, 1101 EFX_WOL_TYPE_MAGIC, 1102 EFX_WOL_TYPE_BITMAP, 1103 EFX_WOL_TYPE_LINK, 1104 EFX_WOL_NTYPES, 1105} efx_wol_type_t; 1106 1107typedef enum efx_lightsout_offload_type_e { 1108 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID, 1109 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP, 1110 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS, 1111} efx_lightsout_offload_type_t; 1112 1113#define EFX_WOL_BITMAP_MASK_SIZE (48) 1114#define EFX_WOL_BITMAP_VALUE_SIZE (128) 1115 1116typedef union efx_wol_param_u { 1117 struct { 1118 uint8_t mac_addr[6]; 1119 } ewp_magic; 1120 struct { 1121 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */ 1122 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */ 1123 uint8_t value_len; 1124 } ewp_bitmap; 1125} efx_wol_param_t; 1126 1127typedef union efx_lightsout_offload_param_u { 1128 struct { 1129 uint8_t mac_addr[6]; 1130 uint32_t ip; 1131 } elop_arp; 1132 struct { 1133 uint8_t mac_addr[6]; 1134 uint32_t solicited_node[4]; 1135 uint32_t ip[4]; 1136 } elop_ns; 1137} efx_lightsout_offload_param_t; 1138 1139extern __checkReturn int 1140efx_wol_init( 1141 __in efx_nic_t *enp); 1142 1143extern __checkReturn int 1144efx_wol_filter_clear( 1145 __in efx_nic_t *enp); 1146 1147extern __checkReturn int 1148efx_wol_filter_add( 1149 __in efx_nic_t *enp, 1150 __in efx_wol_type_t type, 1151 __in efx_wol_param_t *paramp, 1152 __out uint32_t *filter_idp); 1153 1154extern __checkReturn int 1155efx_wol_filter_remove( 1156 __in efx_nic_t *enp, 1157 __in uint32_t filter_id); 1158 1159extern __checkReturn int 1160efx_lightsout_offload_add( 1161 __in efx_nic_t *enp, 1162 __in efx_lightsout_offload_type_t type, 1163 __in efx_lightsout_offload_param_t *paramp, 1164 __out uint32_t *filter_idp); 1165 1166extern __checkReturn int 1167efx_lightsout_offload_remove( 1168 __in efx_nic_t *enp, 1169 __in efx_lightsout_offload_type_t type, 1170 __in uint32_t filter_id); 1171 1172extern void 1173efx_wol_fini( 1174 __in efx_nic_t *enp); 1175 1176#endif /* EFSYS_OPT_WOL */ 1177 1178#if EFSYS_OPT_DIAG 1179 1180typedef enum efx_pattern_type_t { 1181 EFX_PATTERN_BYTE_INCREMENT = 0, 1182 EFX_PATTERN_ALL_THE_SAME, 1183 EFX_PATTERN_BIT_ALTERNATE, 1184 EFX_PATTERN_BYTE_ALTERNATE, 1185 EFX_PATTERN_BYTE_CHANGING, 1186 EFX_PATTERN_BIT_SWEEP, 1187 EFX_PATTERN_NTYPES 1188} efx_pattern_type_t; 1189 1190typedef void 1191(*efx_sram_pattern_fn_t)( 1192 __in size_t row, 1193 __in boolean_t negate, 1194 __out efx_qword_t *eqp); 1195 1196extern __checkReturn int 1197efx_sram_test( 1198 __in efx_nic_t *enp, 1199 __in efx_pattern_type_t type); 1200 1201#endif /* EFSYS_OPT_DIAG */ 1202 1203extern __checkReturn int 1204efx_sram_buf_tbl_set( 1205 __in efx_nic_t *enp, 1206 __in uint32_t id, 1207 __in efsys_mem_t *esmp, 1208 __in size_t n); 1209 1210extern void 1211efx_sram_buf_tbl_clear( 1212 __in efx_nic_t *enp, 1213 __in uint32_t id, 1214 __in size_t n); 1215 1216#define EFX_BUF_TBL_SIZE 0x20000 1217 1218#define EFX_BUF_SIZE 4096 1219 1220/* EV */ 1221 1222typedef struct efx_evq_s efx_evq_t; 1223 1224#if EFSYS_OPT_QSTATS 1225 1226/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */ 1227typedef enum efx_ev_qstat_e { 1228 EV_ALL, 1229 EV_RX, 1230 EV_RX_OK, 1231 EV_RX_RECOVERY, 1232 EV_RX_FRM_TRUNC, 1233 EV_RX_TOBE_DISC, 1234 EV_RX_PAUSE_FRM_ERR, 1235 EV_RX_BUF_OWNER_ID_ERR, 1236 EV_RX_IPV4_HDR_CHKSUM_ERR, 1237 EV_RX_TCP_UDP_CHKSUM_ERR, 1238 EV_RX_ETH_CRC_ERR, 1239 EV_RX_IP_FRAG_ERR, 1240 EV_RX_MCAST_PKT, 1241 EV_RX_MCAST_HASH_MATCH, 1242 EV_RX_TCP_IPV4, 1243 EV_RX_TCP_IPV6, 1244 EV_RX_UDP_IPV4, 1245 EV_RX_UDP_IPV6, 1246 EV_RX_OTHER_IPV4, 1247 EV_RX_OTHER_IPV6, 1248 EV_RX_NON_IP, 1249 EV_RX_OVERRUN, 1250 EV_TX, 1251 EV_TX_WQ_FF_FULL, 1252 EV_TX_PKT_ERR, 1253 EV_TX_PKT_TOO_BIG, 1254 EV_TX_UNEXPECTED, 1255 EV_GLOBAL, 1256 EV_GLOBAL_PHY, 1257 EV_GLOBAL_MNT, 1258 EV_GLOBAL_RX_RECOVERY, 1259 EV_DRIVER, 1260 EV_DRIVER_SRM_UPD_DONE, 1261 EV_DRIVER_TX_DESCQ_FLS_DONE, 1262 EV_DRIVER_RX_DESCQ_FLS_DONE, 1263 EV_DRIVER_RX_DESCQ_FLS_FAILED, 1264 EV_DRIVER_RX_DSC_ERROR, 1265 EV_DRIVER_TX_DSC_ERROR, 1266 EV_DRV_GEN, 1267 EV_MCDI_RESPONSE, 1268 EV_NQSTATS 1269} efx_ev_qstat_t; 1270 1271/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 1272 1273#endif /* EFSYS_OPT_QSTATS */ 1274 1275extern __checkReturn int 1276efx_ev_init( 1277 __in efx_nic_t *enp); 1278 1279extern void 1280efx_ev_fini( 1281 __in efx_nic_t *enp); 1282 1283#define EFX_MASK(_max, _min) (-((_max) << 1) ^ -(_min)) 1284 1285#define EFX_EVQ_MAXNEVS 32768 1286#define EFX_EVQ_MINNEVS 512 1287 1288#define EFX_EVQ_NEVS_MASK EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS) 1289 1290#define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) 1291#define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) 1292 1293extern __checkReturn int 1294efx_ev_qcreate( 1295 __in efx_nic_t *enp, 1296 __in unsigned int index, 1297 __in efsys_mem_t *esmp, 1298 __in size_t n, 1299 __in uint32_t id, 1300 __deref_out efx_evq_t **eepp); 1301 1302extern void 1303efx_ev_qpost( 1304 __in efx_evq_t *eep, 1305 __in uint16_t data); 1306 1307typedef __checkReturn boolean_t 1308(*efx_initialized_ev_t)( 1309 __in_opt void *arg); 1310 1311#define EFX_PKT_UNICAST 0x0004 1312#define EFX_PKT_START 0x0008 1313 1314#define EFX_PKT_VLAN_TAGGED 0x0010 1315#define EFX_CKSUM_TCPUDP 0x0020 1316#define EFX_CKSUM_IPV4 0x0040 1317#define EFX_PKT_CONT 0x0080 1318 1319#define EFX_CHECK_VLAN 0x0100 1320#define EFX_PKT_TCP 0x0200 1321#define EFX_PKT_UDP 0x0400 1322#define EFX_PKT_IPV4 0x0800 1323 1324#define EFX_PKT_IPV6 0x1000 1325#define EFX_ADDR_MISMATCH 0x4000 1326#define EFX_DISCARD 0x8000 1327 1328#define EFX_EV_RX_NLABELS 32 1329#define EFX_EV_TX_NLABELS 32 1330 1331typedef __checkReturn boolean_t 1332(*efx_rx_ev_t)( 1333 __in_opt void *arg, 1334 __in uint32_t label, 1335 __in uint32_t id, 1336 __in uint32_t size, 1337 __in uint16_t flags); 1338 1339typedef __checkReturn boolean_t 1340(*efx_tx_ev_t)( 1341 __in_opt void *arg, 1342 __in uint32_t label, 1343 __in uint32_t id); 1344 1345#define EFX_EXCEPTION_RX_RECOVERY 0x00000001 1346#define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 1347#define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 1348#define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 1349#define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 1350#define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 1351 1352typedef __checkReturn boolean_t 1353(*efx_exception_ev_t)( 1354 __in_opt void *arg, 1355 __in uint32_t label, 1356 __in uint32_t data); 1357 1358typedef __checkReturn boolean_t 1359(*efx_rxq_flush_done_ev_t)( 1360 __in_opt void *arg, 1361 __in uint32_t label); 1362 1363typedef __checkReturn boolean_t 1364(*efx_rxq_flush_failed_ev_t)( 1365 __in_opt void *arg, 1366 __in uint32_t label); 1367 1368typedef __checkReturn boolean_t 1369(*efx_txq_flush_done_ev_t)( 1370 __in_opt void *arg, 1371 __in uint32_t label); 1372 1373typedef __checkReturn boolean_t 1374(*efx_software_ev_t)( 1375 __in_opt void *arg, 1376 __in uint16_t magic); 1377 1378typedef __checkReturn boolean_t 1379(*efx_sram_ev_t)( 1380 __in_opt void *arg, 1381 __in uint32_t code); 1382 1383#define EFX_SRAM_CLEAR 0 1384#define EFX_SRAM_UPDATE 1 1385#define EFX_SRAM_ILLEGAL_CLEAR 2 1386 1387typedef __checkReturn boolean_t 1388(*efx_wake_up_ev_t)( 1389 __in_opt void *arg, 1390 __in uint32_t label); 1391 1392typedef __checkReturn boolean_t 1393(*efx_timer_ev_t)( 1394 __in_opt void *arg, 1395 __in uint32_t label); 1396 1397typedef __checkReturn boolean_t 1398(*efx_link_change_ev_t)( 1399 __in_opt void *arg, 1400 __in efx_link_mode_t link_mode); 1401 1402#if EFSYS_OPT_MON_STATS 1403 1404typedef __checkReturn boolean_t 1405(*efx_monitor_ev_t)( 1406 __in_opt void *arg, 1407 __in efx_mon_stat_t id, 1408 __in efx_mon_stat_value_t value); 1409 1410#endif /* EFSYS_OPT_MON_STATS */ 1411 1412#if EFSYS_OPT_MAC_STATS 1413 1414typedef __checkReturn boolean_t 1415(*efx_mac_stats_ev_t)( 1416 __in_opt void *arg, 1417 __in uint32_t generation 1418 ); 1419 1420#endif /* EFSYS_OPT_MAC_STATS */ 1421 1422typedef struct efx_ev_callbacks_s { 1423 efx_initialized_ev_t eec_initialized; 1424 efx_rx_ev_t eec_rx; 1425 efx_tx_ev_t eec_tx; 1426 efx_exception_ev_t eec_exception; 1427 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 1428 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 1429 efx_txq_flush_done_ev_t eec_txq_flush_done; 1430 efx_software_ev_t eec_software; 1431 efx_sram_ev_t eec_sram; 1432 efx_wake_up_ev_t eec_wake_up; 1433 efx_timer_ev_t eec_timer; 1434 efx_link_change_ev_t eec_link_change; 1435#if EFSYS_OPT_MON_STATS 1436 efx_monitor_ev_t eec_monitor; 1437#endif /* EFSYS_OPT_MON_STATS */ 1438#if EFSYS_OPT_MAC_STATS 1439 efx_mac_stats_ev_t eec_mac_stats; 1440#endif /* EFSYS_OPT_MON_STATS */ 1441} efx_ev_callbacks_t; 1442 1443extern __checkReturn boolean_t 1444efx_ev_qpending( 1445 __in efx_evq_t *eep, 1446 __in unsigned int count); 1447 1448#if EFSYS_OPT_EV_PREFETCH 1449 1450extern void 1451efx_ev_qprefetch( 1452 __in efx_evq_t *eep, 1453 __in unsigned int count); 1454 1455#endif /* EFSYS_OPT_EV_PREFETCH */ 1456 1457extern void 1458efx_ev_qpoll( 1459 __in efx_evq_t *eep, 1460 __inout unsigned int *countp, 1461 __in const efx_ev_callbacks_t *eecp, 1462 __in_opt void *arg); 1463 1464extern __checkReturn int 1465efx_ev_qmoderate( 1466 __in efx_evq_t *eep, 1467 __in unsigned int us); 1468 1469extern __checkReturn int 1470efx_ev_qprime( 1471 __in efx_evq_t *eep, 1472 __in unsigned int count); 1473 1474#if EFSYS_OPT_QSTATS 1475 1476#if EFSYS_OPT_NAMES 1477 1478extern const char __cs * 1479efx_ev_qstat_name( 1480 __in efx_nic_t *enp, 1481 __in unsigned int id); 1482 1483#endif /* EFSYS_OPT_NAMES */ 1484 1485extern void 1486efx_ev_qstats_update( 1487 __in efx_evq_t *eep, 1488 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 1489 1490#endif /* EFSYS_OPT_QSTATS */ 1491 1492extern void 1493efx_ev_qdestroy( 1494 __in efx_evq_t *eep); 1495 1496/* RX */ 1497 1498typedef struct efx_rxq_s efx_rxq_t; 1499 1500extern __checkReturn int 1501efx_rx_init( 1502 __in efx_nic_t *enp); 1503 1504extern void 1505efx_rx_fini( 1506 __in efx_nic_t *enp); 1507 1508#if EFSYS_OPT_RX_HDR_SPLIT 1509 __checkReturn int 1510efx_rx_hdr_split_enable( 1511 __in efx_nic_t *enp, 1512 __in unsigned int hdr_buf_size, 1513 __in unsigned int pld_buf_size); 1514 1515#endif /* EFSYS_OPT_RX_HDR_SPLIT */ 1516 1517#if EFSYS_OPT_RX_SCATTER 1518 __checkReturn int 1519efx_rx_scatter_enable( 1520 __in efx_nic_t *enp, 1521 __in unsigned int buf_size); 1522#endif /* EFSYS_OPT_RX_SCATTER */ 1523 1524#if EFSYS_OPT_RX_SCALE 1525 1526typedef enum efx_rx_hash_alg_e { 1527 EFX_RX_HASHALG_LFSR = 0, 1528 EFX_RX_HASHALG_TOEPLITZ 1529} efx_rx_hash_alg_t; 1530 1531typedef enum efx_rx_hash_type_e { 1532 EFX_RX_HASH_IPV4 = 0, 1533 EFX_RX_HASH_TCPIPV4, 1534 EFX_RX_HASH_IPV6, 1535 EFX_RX_HASH_TCPIPV6, 1536} efx_rx_hash_type_t; 1537 1538#define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 1539#define EFX_MAXRSS 64 /* RX indirection entry range */ 1540#define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 1541 1542extern __checkReturn int 1543efx_rx_scale_mode_set( 1544 __in efx_nic_t *enp, 1545 __in efx_rx_hash_alg_t alg, 1546 __in efx_rx_hash_type_t type, 1547 __in boolean_t insert); 1548 1549extern __checkReturn int 1550efx_rx_scale_tbl_set( 1551 __in efx_nic_t *enp, 1552 __in_ecount(n) unsigned int *table, 1553 __in size_t n); 1554 1555extern __checkReturn int 1556efx_rx_scale_toeplitz_ipv4_key_set( 1557 __in efx_nic_t *enp, 1558 __in_ecount(n) uint8_t *key, 1559 __in size_t n); 1560 1561extern __checkReturn int 1562efx_rx_scale_toeplitz_ipv6_key_set( 1563 __in efx_nic_t *enp, 1564 __in_ecount(n) uint8_t *key, 1565 __in size_t n); 1566 1567/* 1568 * The prefix is a byte array of one of the forms: 1569 * 1570 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1571 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT 1572 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL 1573 * 1574 * where: 1575 * 1576 * TT.TT.TT.TT is a 32-bit Toeplitz hash 1577 * LL.LL is a 16-bit LFSR hash 1578 * 1579 * Hash values are in network (big-endian) byte order. 1580 */ 1581 1582#define EFX_RX_PREFIX_SIZE 16 1583 1584#define EFX_RX_HASH_VALUE(_func, _buffer) \ 1585 (((_func) == EFX_RX_HASHALG_LFSR) ? \ 1586 ((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) : \ 1587 ((uint32_t)(((_buffer)[12] << 24) | \ 1588 ((_buffer)[13] << 16) | \ 1589 ((_buffer)[14] << 8) | \ 1590 (_buffer)[15]))) 1591 1592#define EFX_RX_HASH_SIZE(_func) \ 1593 (((_func) == EFX_RX_HASHALG_LFSR) ? \ 1594 sizeof (uint16_t) : \ 1595 sizeof (uint32_t)) 1596 1597#endif /* EFSYS_OPT_RX_SCALE */ 1598 1599#define EFX_RXQ_MAXNDESCS 4096 1600#define EFX_RXQ_MINNDESCS 512 1601 1602#define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS) 1603 1604#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1605#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1606#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1607 1608typedef enum efx_rxq_type_e { 1609 EFX_RXQ_TYPE_DEFAULT, 1610 EFX_RXQ_TYPE_SPLIT_HEADER, 1611 EFX_RXQ_TYPE_SPLIT_PAYLOAD, 1612 EFX_RXQ_TYPE_SCATTER, 1613 EFX_RXQ_NTYPES 1614} efx_rxq_type_t; 1615 1616extern __checkReturn int 1617efx_rx_qcreate( 1618 __in efx_nic_t *enp, 1619 __in unsigned int index, 1620 __in unsigned int label, 1621 __in efx_rxq_type_t type, 1622 __in efsys_mem_t *esmp, 1623 __in size_t n, 1624 __in uint32_t id, 1625 __in efx_evq_t *eep, 1626 __deref_out efx_rxq_t **erpp); 1627 1628typedef struct efx_buffer_s { 1629 efsys_dma_addr_t eb_addr; 1630 size_t eb_size; 1631 boolean_t eb_eop; 1632} efx_buffer_t; 1633 1634extern void 1635efx_rx_qpost( 1636 __in efx_rxq_t *erp, 1637 __in_ecount(n) efsys_dma_addr_t *addrp, 1638 __in size_t size, 1639 __in unsigned int n, 1640 __in unsigned int completed, 1641 __in unsigned int added); 1642 1643extern void 1644efx_rx_qpush( 1645 __in efx_rxq_t *erp, 1646 __in unsigned int added); 1647 1648extern void 1649efx_rx_qflush( 1650 __in efx_rxq_t *erp); 1651 1652extern void 1653efx_rx_qenable( 1654 __in efx_rxq_t *erp); 1655 1656extern void 1657efx_rx_qdestroy( 1658 __in efx_rxq_t *erp); 1659 1660/* TX */ 1661 1662typedef struct efx_txq_s efx_txq_t; 1663 1664#if EFSYS_OPT_QSTATS 1665 1666/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */ 1667typedef enum efx_tx_qstat_e { 1668 TX_POST, 1669 TX_UNALIGNED_SPLIT, 1670 TX_NQSTATS 1671} efx_tx_qstat_t; 1672 1673/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 1674 1675#endif /* EFSYS_OPT_QSTATS */ 1676 1677extern __checkReturn int 1678efx_tx_init( 1679 __in efx_nic_t *enp); 1680 1681extern void 1682efx_tx_fini( 1683 __in efx_nic_t *enp); 1684 1685#define EFX_TXQ_MAXNDESCS 4096 1686#define EFX_TXQ_MINNDESCS 512 1687 1688#define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS) 1689 1690#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t)) 1691#define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE) 1692#define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 1693 1694extern __checkReturn int 1695efx_tx_qcreate( 1696 __in efx_nic_t *enp, 1697 __in unsigned int index, 1698 __in unsigned int label, 1699 __in efsys_mem_t *esmp, 1700 __in size_t n, 1701 __in uint32_t id, 1702 __in uint16_t flags, 1703 __in efx_evq_t *eep, 1704 __deref_out efx_txq_t **etpp); 1705 1706extern __checkReturn int 1707efx_tx_qpost( 1708 __in efx_txq_t *etp, 1709 __in_ecount(n) efx_buffer_t *eb, 1710 __in unsigned int n, 1711 __in unsigned int completed, 1712 __inout unsigned int *addedp); 1713 1714extern void 1715efx_tx_qpush( 1716 __in efx_txq_t *etp, 1717 __in unsigned int added); 1718 1719extern void 1720efx_tx_qflush( 1721 __in efx_txq_t *etp); 1722 1723extern void 1724efx_tx_qenable( 1725 __in efx_txq_t *etp); 1726 1727#if EFSYS_OPT_QSTATS 1728 1729#if EFSYS_OPT_NAMES 1730 1731extern const char __cs * 1732efx_tx_qstat_name( 1733 __in efx_nic_t *etp, 1734 __in unsigned int id); 1735 1736#endif /* EFSYS_OPT_NAMES */ 1737 1738extern void 1739efx_tx_qstats_update( 1740 __in efx_txq_t *etp, 1741 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 1742 1743#endif /* EFSYS_OPT_QSTATS */ 1744 1745extern void 1746efx_tx_qdestroy( 1747 __in efx_txq_t *etp); 1748 1749 1750/* FILTER */ 1751 1752#if EFSYS_OPT_FILTER 1753 1754typedef enum efx_filter_flag_e { 1755 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across 1756 * multiple queues */ 1757 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */ 1758 EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04, /* MAC filter overrides 1759 * any matching IP filter */ 1760} efx_filter_flag_t; 1761 1762typedef struct efx_filter_spec_s { 1763 uint8_t efs_type; 1764 uint8_t efs_flags; 1765 uint16_t efs_dmaq_id; 1766 uint32_t efs_dword[3]; 1767} efx_filter_spec_t; 1768 1769extern __checkReturn int 1770efx_filter_init( 1771 __in efx_nic_t *enp); 1772 1773extern void 1774efx_filter_fini( 1775 __in efx_nic_t *enp); 1776 1777extern __checkReturn int 1778efx_rx_filter_insert( 1779 __in efx_rxq_t *erp, 1780 __inout efx_filter_spec_t *spec); 1781 1782extern __checkReturn int 1783efx_rx_filter_remove( 1784 __in efx_rxq_t *erp, 1785 __inout efx_filter_spec_t *spec); 1786 1787 void 1788efx_filter_restore( 1789 __in efx_nic_t *enp); 1790 1791extern void 1792efx_filter_spec_rx_ipv4_tcp_full( 1793 __inout efx_filter_spec_t *spec, 1794 __in unsigned int flags, 1795 __in uint32_t src_ip, 1796 __in uint16_t src_tcp, 1797 __in uint32_t dest_ip, 1798 __in uint16_t dest_tcp); 1799 1800extern void 1801efx_filter_spec_rx_ipv4_tcp_wild( 1802 __inout efx_filter_spec_t *spec, 1803 __in unsigned int flags, 1804 __in uint32_t dest_ip, 1805 __in uint16_t dest_tcp); 1806 1807extern void 1808efx_filter_spec_rx_ipv4_udp_full( 1809 __inout efx_filter_spec_t *spec, 1810 __in unsigned int flags, 1811 __in uint32_t src_ip, 1812 __in uint16_t src_udp, 1813 __in uint32_t dest_ip, 1814 __in uint16_t dest_udp); 1815 1816extern void 1817efx_filter_spec_rx_ipv4_udp_wild( 1818 __inout efx_filter_spec_t *spec, 1819 __in unsigned int flags, 1820 __in uint32_t dest_ip, 1821 __in uint16_t dest_udp); 1822 1823extern void 1824efx_filter_spec_rx_mac_full( 1825 __inout efx_filter_spec_t *spec, 1826 __in unsigned int flags, 1827 __in uint16_t vlan_id, 1828 __in uint8_t *dest_mac); 1829 1830extern void 1831efx_filter_spec_rx_mac_wild( 1832 __inout efx_filter_spec_t *spec, 1833 __in unsigned int flags, 1834 __in uint8_t *dest_mac); 1835 1836 1837extern __checkReturn int 1838efx_tx_filter_insert( 1839 __in efx_txq_t *etp, 1840 __inout efx_filter_spec_t *spec); 1841 1842extern __checkReturn int 1843efx_tx_filter_remove( 1844 __in efx_txq_t *etp, 1845 __inout efx_filter_spec_t *spec); 1846 1847extern void 1848efx_filter_spec_tx_ipv4_tcp_full( 1849 __inout efx_filter_spec_t *spec, 1850 __in uint32_t src_ip, 1851 __in uint16_t src_tcp, 1852 __in uint32_t dest_ip, 1853 __in uint16_t dest_tcp); 1854 1855extern void 1856efx_filter_spec_tx_ipv4_tcp_wild( 1857 __inout efx_filter_spec_t *spec, 1858 __in uint32_t src_ip, 1859 __in uint16_t src_tcp); 1860 1861extern void 1862efx_filter_spec_tx_ipv4_udp_full( 1863 __inout efx_filter_spec_t *spec, 1864 __in uint32_t src_ip, 1865 __in uint16_t src_udp, 1866 __in uint32_t dest_ip, 1867 __in uint16_t dest_udp); 1868 1869extern void 1870efx_filter_spec_tx_ipv4_udp_wild( 1871 __inout efx_filter_spec_t *spec, 1872 __in uint32_t src_ip, 1873 __in uint16_t src_udp); 1874 1875extern void 1876efx_filter_spec_tx_mac_full( 1877 __inout efx_filter_spec_t *spec, 1878 __in uint16_t vlan_id, 1879 __in uint8_t *src_mac); 1880 1881extern void 1882efx_filter_spec_tx_mac_wild( 1883 __inout efx_filter_spec_t *spec, 1884 __in uint8_t *src_mac); 1885 1886#endif /* EFSYS_OPT_FILTER */ 1887 1888 1889#ifdef __cplusplus 1890} 1891#endif 1892 1893#endif /* _SYS_EFX_H */ 1894