1/* 2 * Copyright (c) 2014, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8/* 9 * 10 * 11 */ 12#include <stdio.h> 13#include <string.h> 14 15#include <barrelfish/barrelfish.h> 16#include <barrelfish/dispatch.h> 17#include <barrelfish/waitset.h> 18#include <barrelfish/nameservice_client.h> 19#include <bench/bench.h> 20 21#include <dma/dma.h> 22#include <dma/dma_request.h> 23#include <dma/dma_bench.h> 24#include <dma/client/dma_client_device.h> 25#include <dma/dma_manager_client.h> 26 27#define BENCH_XEON_PHI_DMA 0 28#define BENCH_XEON_PHI_DMA_BASE (4UL * 1024 * 1024 * 1024) 29#define BENCH_XEON_PHI_DMA_BASE2 (5UL * 1024 * 1024 * 1024) 30 31#define DMA_BUFFER_SIZE 28 32#define DMA_BUFFER_COUNT 2 33 34#define EXPECT_SUCCESS(err, msg) if (err_is_fail(err)) {USER_PANIC_ERR(err, msg);} 35 36static struct capref frame; 37static size_t frame_size; 38static lpaddr_t frame_addr; 39static void *frame_virt; 40 41#ifndef __k1om__ 42static struct capref frame2; 43static size_t frame_size2; 44static lpaddr_t frame_addr2; 45static void *frame_virt2; 46#endif 47 48static uint8_t *buffers[2*DMA_BUFFER_COUNT]; 49static lpaddr_t phys[2*DMA_BUFFER_COUNT]; 50 51static void prepare(void) 52{ 53 errval_t err; 54 55 debug_printf("Preparing resources...\n"); 56 57 ram_set_affinity(0, (128UL * 1024 * 1024 * 1024)); 58 59 err = frame_alloc(&frame, DMA_BUFFER_COUNT * (1UL << DMA_BUFFER_SIZE), 60 &frame_size); 61 EXPECT_SUCCESS(err, "allocating frame"); 62 63 struct frame_identity id; 64 err = invoke_frame_identify(frame, &id); 65 EXPECT_SUCCESS(err, "Frame identify"); 66 67 frame_addr = id.base; 68 69 err = vspace_map_one_frame(&frame_virt, frame_size, frame, NULL, NULL); 70 EXPECT_SUCCESS(err, "Mapping of frame"); 71 72 uint8_t *b = frame_virt; 73 lpaddr_t p = frame_addr; 74 for (uint32_t i = 0; i < DMA_BUFFER_COUNT; ++i) { 75 buffers[i] = b; 76 phys[i] = p; 77 b += ((1UL << DMA_BUFFER_SIZE)); 78 p += ((1UL << DMA_BUFFER_SIZE)); 79 } 80 81#ifndef __k1om__ 82 83 ram_set_affinity((128UL * 1024 * 1024 * 1024), (256UL * 1024 * 1024 * 1024)); 84 85 EXPECT_SUCCESS(err, "allocating frame"); 86 err = frame_alloc(&frame2, DMA_BUFFER_COUNT * (1UL << DMA_BUFFER_SIZE), 87 &frame_size2); 88 struct frame_identity id2; 89 err = invoke_frame_identify(frame2, &id2); 90 EXPECT_SUCCESS(err, "Frame identify"); 91 92 frame_addr2 = id2.base; 93 err = vspace_map_one_frame(&frame_virt2, frame_size2, frame2, NULL, NULL); 94 EXPECT_SUCCESS(err, "Mapping of frame"); 95 96 b = frame_virt2; 97 p = frame_addr2; 98 for (uint32_t i = 0; i < DMA_BUFFER_COUNT; ++i) { 99 buffers[i+DMA_BUFFER_COUNT] = b; 100 phys[i+DMA_BUFFER_COUNT] = p; 101 b += ((1UL << DMA_BUFFER_SIZE)); 102 p += ((1UL << DMA_BUFFER_SIZE)); 103 } 104#endif 105 106 debug_printf("preparation done.\n"); 107} 108 109int main(int argc, 110 char *argv[]) 111{ 112 errval_t err; 113 114 debug_printf("DMA Test domain started\n"); 115 116 prepare(); 117 118 bench_init(); 119 120#if 0 121 char svc_name[30]; 122 uint8_t numa_node = (disp_get_core_id() >= 20); 123 snprintf(svc_name, 30, "ioat_dma_svc.%u", numa_node); 124 iref_t iref; 125 err = nameservice_blocking_lookup(svc_name, &iref); 126#endif 127 128 129 130#ifdef __k1om__ 131 err = dma_manager_wait_for_driver(DMA_DEV_TYPE_XEON_PHI, disp_xeon_phi_id()); 132 EXPECT_SUCCESS(err, "waiting for driver"); 133 struct dma_client_info info = { 134 .type = DMA_CLIENT_INFO_TYPE_NAME, 135 .device_type = DMA_DEV_TYPE_XEON_PHI, 136 .args = { 137 .name = XEON_PHI_DMA_SERVICE_NAME 138 } 139 }; 140#else 141#if BENCH_XEON_PHI_DMA 142 err = dma_manager_wait_for_driver(DMA_DEV_TYPE_XEON_PHI, 1); 143 EXPECT_SUCCESS(err, "waiting for driver"); 144 struct dma_client_info info = { 145 .type = DMA_CLIENT_INFO_TYPE_NAME, 146 .device_type = DMA_DEV_TYPE_XEON_PHI, 147 .args = { 148 .name = "xeon_phi_dma_svc.0" 149 } 150 }; 151#else 152 err = dma_manager_wait_for_driver(DMA_DEV_TYPE_IOAT, 0); 153 EXPECT_SUCCESS(err, "waiting for driver"); 154 struct dma_client_info info = { 155 .type = DMA_CLIENT_INFO_TYPE_NAME, 156 .device_type = DMA_DEV_TYPE_IOAT, 157 .args = { 158 .name = "ioat_dma_svc.0" 159 } 160 }; 161#endif 162#endif 163 164 struct dma_client_device *dev; 165 err = dma_client_device_init(&info, &dev); 166 167 err = dma_register_memory((struct dma_device *)dev, frame); 168 EXPECT_SUCCESS(err, "registering memory\n"); 169 170#ifndef __k1om 171 debug_printf("NUMA 0 -> NUMA 1\n"); 172 // err = dma_bench_run_memcpy(buffers[0], buffers[DMA_BUFFER_COUNT]); 173 EXPECT_SUCCESS(err, "dma_bench_run_memcpy\n"); 174 175 debug_printf("NUMA 1 -> NUMA 0\n"); 176 // err = dma_bench_run_memcpy(buffers[DMA_BUFFER_COUNT], buffers[0]); 177 EXPECT_SUCCESS(err, "dma_bench_run_memcpy\n"); 178#endif 179 debug_printf("Numa 0 -> Numa 0\n"); 180 //err = dma_bench_run_memcpy(buffers[0], buffers[1]); 181 EXPECT_SUCCESS(err, "dma_bench_run_memcpy\n"); 182 183#if BENCH_XEON_PHI_DMA 184 err = dma_bench_run((struct dma_device *)dev, BENCH_XEON_PHI_DMA_BASE, 185 BENCH_XEON_PHI_DMA_BASE2); 186 EXPECT_SUCCESS(err, "dma_bench_run\n"); 187 debug_printf("DMA Benchmark done.\n"); 188 return 0; 189#else 190 err = dma_bench_run((struct dma_device *)dev, phys[0], phys[1]); 191 EXPECT_SUCCESS(err, "dma_bench_run\n"); 192#ifndef __k1om__ 193 err = dma_register_memory((struct dma_device *)dev, frame2); 194 EXPECT_SUCCESS(err, "registering memory\n"); 195 196 debug_printf("Numa 0 -> Numa 1\n"); 197 debug_printf("%lx -> %lx, \n", phys[0], phys[DMA_BUFFER_COUNT]); 198 err = dma_bench_run((struct dma_device *)dev, phys[0], phys[DMA_BUFFER_COUNT]); 199 EXPECT_SUCCESS(err, "dma_bench_run\n"); 200 201 debug_printf("Numa 1 -> Numa 0\n"); 202 err = dma_bench_run((struct dma_device *)dev, phys[DMA_BUFFER_COUNT], phys[0]); 203 EXPECT_SUCCESS(err, "dma_bench_run\n"); 204#endif 205#endif 206 debug_printf("DMA Benchmark done.\n"); 207 208 return 0; 209} 210 211