1
2#include <aboot/aboot.h>
3#include <aboot/io.h>
4#include <omap4/mux.h>
5#include <omap4/hw.h>
6
7/* syslib.c */
8
9void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
10{
11	u32 tmp, msk = 0;
12	msk = 1 << num_bits;
13	--msk;
14	tmp = readl(addr) & ~(msk << start_bit);
15	tmp |=  value << start_bit;
16	writel(tmp, addr);
17}
18
19u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
20{
21	u32 i = 0, val;
22	do {
23		++i;
24		val = readl(read_addr) & read_bit_mask;
25		if (val == match_value)
26			return (1);
27		if (i == bound)
28			return (0);
29	} while (1);
30}
31
32void sdelay(unsigned long loops)
33{
34	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
35			  "bne 1b":"=r" (loops):"0"(loops));
36}
37
38void scale_vcores(void)
39{
40	/* For VC bypass only VCOREx_CGF_FORCE  is necessary and
41	 * VCOREx_CFG_VOLTAGE  changes can be discarded
42	 */
43	/* PRM_VC_CFG_I2C_MODE */
44	writel(0x0, 0x4A307BA8);
45	/* PRM_VC_CFG_I2C_CLK */
46	writel(0x6026, 0x4A307BAC);
47
48	/* set VCORE1 force VSEL */
49	/* PRM_VC_VAL_BYPASS) */
50	writel(0x3A5512, 0x4A307BA0);
51
52	writel(readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
53	while(readl(0x4A307BA0) & 0x1000000)
54		;
55
56	/* PRM_IRQSTATUS_MPU */
57	writel(readl(0x4A306010), 0x4A306010);
58
59
60	/* FIXME: set VCORE2 force VSEL, Check the reset value */
61	/* PRM_VC_VAL_BYPASS) */
62	writel(0x295B12, 0x4A307BA0);
63	writel(readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
64	while(readl(0x4A307BA0) & 0x1000000)
65		;
66
67	/* PRM_IRQSTATUS_MPU */
68	writel(readl(0x4A306010), 0x4A306010);
69
70	/*set VCORE3 force VSEL */
71	/* PRM_VC_VAL_BYPASS */
72	writel(0x2A6112, 0x4A307BA0);
73
74	writel(readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
75
76	while(readl(0x4A307BA0) & 0x1000000)
77		;
78
79	/* PRM_IRQSTATUS_MPU */
80	writel(readl(0x4A306010), 0x4A306010);
81}
82