1# Simple M5 script for use with Barrelfish. This creates a very 2# basic machine with a set of CPUs connected directly to the 3# simulated memory. 4# 5# (See configs/example/* in the M5 distribution for examples of 6# fuller scripts -- caches, etc.). 7 8import optparse 9import os 10import sys 11import m5 12 13from m5.defines import buildEnv 14from m5.objects import * 15from m5.util import fatal 16 17####################################################################### 18# 19# Check that we are running on a full-system X86 simulator 20 21if not buildEnv['FULL_SYSTEM']: 22 fatal("Expected FULL_SYSTEM"); 23 24if not buildEnv['TARGET_ISA'] == "x86": 25 fatal("Expected TARGET_ISA == x86"); 26 27####################################################################### 28# 29# Set up basic configuration options: kernel location and number of 30# CPUs. 31 32parser = optparse.OptionParser() 33parser.add_option("--kernel", action="store", type="string") 34parser.add_option("--num_cpus", action="store", type="int") 35(options, args) = parser.parse_args() 36 37####################################################################### 38# 39# Create simulated machine. 40 41system = X86System() 42 43# Kernel to boot 44system.kernel = options.kernel 45 46# Physical memory 47system.membus = Bus() 48system.physmem = PhysicalMemory(range = AddrRange('512MB')) 49system.physmem.port = system.membus.port 50 51# CPUs 52CPUClass = AtomicSimpleCPU 53CPUClass.clock = '2GHz' 54system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] 55system.mem_mode = 'atomic' 56for i in xrange(options.num_cpus): 57 system.cpu[i].connectAllPorts(system.membus) 58 system.intel_mp_table.add_entry( 59 X86IntelMPProcessor(local_apic_id = i, 60 local_apic_version = 0x14, 61 enable = True, 62 bootstrap = (i == 0))) 63 64# North Bridge 65system.iobus = Bus(bus_id=0) 66system.bridge = Bridge(delay='50ns', nack_delay='4ns') 67system.bridge.side_a = system.iobus.port 68system.bridge.side_b = system.membus.port 69 70# Platform 71system.pc = Pc() 72system.pc.attachIO(system.iobus) 73system.intrctrl = IntrControl() 74 75# APIC and devices 76io_apic = X86IntelMPIOAPIC(id = options.num_cpus, 77 version = 0x11, 78 enable = True, 79 address = 0xfec00000) 80system.pc.south_bridge.io_apic.apic_id = io_apic.id 81system.intel_mp_table.add_entry(io_apic) 82 83connect_busses = X86IntelMPBusHierarchy(bus_id=0, 84 subtractive_decode=True, 85 parent_bus=1) 86system.intel_mp_table.add_entry(connect_busses) 87 88pci_dev4_inta = X86IntelMPIOIntAssignment( 89 interrupt_type = 'INT', 90 polarity = 'ConformPolarity', 91 trigger = 'ConformTrigger', 92 source_bus_id = 1, 93 source_bus_irq = 0 + (4 << 2), 94 dest_io_apic_id = io_apic.id, 95 dest_io_apic_intin = 16) 96 97system.intel_mp_table.add_entry(pci_dev4_inta); 98 99####################################################################### 100# 101# Start simulation 102 103Root(system=system) 104m5.instantiate() 105 106print '..... STARTING SIMULATION' 107 108exit_event = m5.simulate() 109exit_cause = exit_event.getCause() 110 111print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_cause) 112 113 114 115 116 117